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IS61VPS102418-200B2 PDF预览

IS61VPS102418-200B2

更新时间： 2024-11-27 15:35:31
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
29页 166K
描述
Cache SRAM, 1MX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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IS61VPS102418-200B2 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.78
最长访问时间：3.1 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX18封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：2.41 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

IS61VPS102418-200B2 数据手册

 浏览型号IS61VPS102418-200B2的Datasheet PDF文件第2页浏览型号IS61VPS102418-200B2的Datasheet PDF文件第3页浏览型号IS61VPS102418-200B2的Datasheet PDF文件第4页浏览型号IS61VPS102418-200B2的Datasheet PDF文件第5页浏览型号IS61VPS102418-200B2的Datasheet PDF文件第6页浏览型号IS61VPS102418-200B2的Datasheet PDF文件第7页 
®
IS61VPS51236A IS61VPS102418A  
IS61LPS51236A IS61LPS102418A  
ISSI  
512K x 36, 1024K x 18  
18Mb SYNCHRONOUS PIPELINED,  
SINGLE CYCLE DESELECT STATIC RAM  
ADVANCE INFORMATION  
DECEMBER 2002  
DESCRIPTION  
FEATURES  
The ISSI IS61LPS/VPS51236A and IS61LPS/  
VPS102418Aarehigh-speed,low-powersynchronousstatic  
RAMsdesignedtoprovideburstable,high-performancememory  
for communication and networking applications. The  
IS61LPS/VPS51236Aisorganizedas524,288wordsby36  
bits, and the IS61LPS/VPS102418A is organized as  
1,048,576 words by 18 bits. Fabricated with ISSI's ad-  
vanced CMOS technology, the device integrates a 2-bit  
burst counter, high-speed SRAM core, and high-drive  
capability outputs into a single monolithic circuit. All  
synchronous inputs pass through registers controlled by  
a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
• Three chip enable option for simple depth  
expansion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be one  
to four bytes wide as controlled by the write control inputs.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• Power Supply  
Separate byte enables allow individual bytes to be written.  
The byte write operation is performed by using the byte  
write enable (BWE) input combined with one or more  
individual byte write signals (BWx). In addition, Global  
Write (GW) is available for writing all bytes at one time,  
regardless of the byte write controls.  
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
• JEDEC 100-Pin TQFP,  
119-pin PBGA, and 165-pin PBGA package  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
250  
2.6  
4
200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best  
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
ADVANCEINFORMATION Rev. 00A  
1
12/17/02  
1234567...29

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与IS61VPS102418-200B2相关器件

型号 品牌 获取价格 描述 数据表
IS61VPS102418-200B2I ISSI

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 		Cache SRAM, 1MX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IS61VPS102418-200B3 ISSI

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 		Cache SRAM, 1MX18, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
IS61VPS102418-200B3I ISSI

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 		Cache SRAM, 1MX18, 3.1ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
IS61VPS102418-200TQ ISSI

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 		Cache SRAM, 1MX18, 3.1ns, CMOS, PQFP100, TQFP-100
IS61VPS102418-250B2 ISSI

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 		Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IS61VPS102418-250B2I ISSI

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 		Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IS61VPS102418-250B3 ISSI

获取价格

 		Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
IS61VPS102418-250TQ ISSI

获取价格

 		Cache SRAM, 1MX18, 2.6ns, CMOS, PQFP100, TQFP-100
IS61VPS102418-250TQI ISSI

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 		Cache SRAM, 1MX18, 2.6ns, CMOS, PQFP100, TQFP-100
IS61VPS102418A ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC

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