Datasheet > IS61VPD51236A

IS61VPD51236A

更新时间： 2024-11-27 04:44:47

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
29页	208K
描述
512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS61VPD51236A 数据手册

IS61VPD51236A IS61VPD102418A

IS61LPD51236A IS61LPD102418A

ISSI

512K x 36, 1024K x 18

18Mb SYNCHRONOUS PIPELINED,

DOUBLE CYCLE DESELECT STATIC RAM

FEBRUARY 2006

DESCRIPTION

FEATURES

The ISSI IS61LPD/VPD51236A and IS61LPD/

VPD102418Aarehigh-speed,low-powersynchronousstatic

RAMsdesignedtoprovideburstable,high-performancememory

for communication and networking applications. The

IS61LPD/VPD51236Aisorganizedas524,288wordsby36

bits, and the IS61LPD/VPD102418A is organized as

1,048,576 words by 18 bits. Fabricated with ISSI's ad-

vanced CMOS technology, the device integrates a 2-bit

burstcounter,high-speedSRAMcore,andhigh-drivecapa-

bility outputs into a single monolithic circuit. All synchro-

nousinputspassthroughregisterscontrolledbyapositive-

edge-triggeredsingleclockinput.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Double cycle deselect

Writecyclesareinternallyself-timedandareinitiatedbythe

risingedgeoftheclockinput.Writecyclescanbeonetofour

bytes wide as controlled by the write control inputs.

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). In addition, Global

Write (GW) is available for writing all bytes at one time,

regardless of the byte write controls.

LPD: V^DD3.3V + 5%, VDDQ 3.3V/2.5V + 5%

VPD: V^DD2.5V + 5%, VDDQ 2.5V + 5%

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address

advance) input pin.

• JEDEC 100-Pin TQFP and 165-pin PBGA

package

• Lead-free available

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

250

2.6

200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

02/03/06

12 3 4 5 6 7...29

中文翻译

下载PDF

与IS61VPD51236A相关器件

型号	品牌	获取价格	描述	数据表
IS61VPD51236A-200B3	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-200B3I	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-200TQ	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-200TQI	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-250B3	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-250B3I	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-250TQ	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-250TQI	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPS10018-166BI	ISSI	获取价格	Cache SRAM, 1MX18, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61VPS10018-166TQ	ISSI	获取价格	Cache SRAM, 1MX18, 3.5ns, CMOS, PQFP100, TQFP-100

与IS61VPD51236A相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

46
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

35
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

64
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

61

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61VPD51236A

IS61VPD51236A 数据手册

与IS61VPD51236A相关器件

与IS61VPD51236A相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61VPD51236A

IS61VPD51236A 数据手册

与IS61VPD51236A相关器件

与IS61VPD51236A相关文章

您还可以找

您在本页遇到什么问题？