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IS61VPD51236A-200B3 PDF预览

IS61VPD51236A-200B3

更新时间： 2024-11-27 04:44:47
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
29页 208K
描述
512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

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IS61VPD51236A-200B3 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：BGA
包装说明：TBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41Factory Lead Time：10 weeks
风险等级：5.55Is Samacsys：N
最长访问时间：3.1 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：36
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.06 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.425 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：13 mmBase Number Matches：1

IS61VPD51236A-200B3 数据手册

 浏览型号IS61VPD51236A-200B3的Datasheet PDF文件第2页浏览型号IS61VPD51236A-200B3的Datasheet PDF文件第3页浏览型号IS61VPD51236A-200B3的Datasheet PDF文件第4页浏览型号IS61VPD51236A-200B3的Datasheet PDF文件第5页浏览型号IS61VPD51236A-200B3的Datasheet PDF文件第6页浏览型号IS61VPD51236A-200B3的Datasheet PDF文件第7页 
®
IS61VPD51236A IS61VPD102418A  
IS61LPD51236A IS61LPD102418A  
ISSI  
512K x 36, 1024K x 18  
18Mb SYNCHRONOUS PIPELINED,  
DOUBLE CYCLE DESELECT STATIC RAM  
FEBRUARY 2006  
DESCRIPTION  
FEATURES  
The ISSI IS61LPD/VPD51236A and IS61LPD/  
VPD102418Aarehigh-speed,low-powersynchronousstatic  
RAMsdesignedtoprovideburstable,high-performancememory  
for communication and networking applications. The  
IS61LPD/VPD51236Aisorganizedas524,288wordsby36  
bits, and the IS61LPD/VPD102418A is organized as  
1,048,576 words by 18 bits. Fabricated with ISSI's ad-  
vanced CMOS technology, the device integrates a 2-bit  
burstcounter,high-speedSRAMcore,andhigh-drivecapa-  
bility outputs into a single monolithic circuit. All synchro-  
nousinputspassthroughregisterscontrolledbyapositive-  
edge-triggeredsingleclockinput.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
• Three chip enable option for simple depth  
expansion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Double cycle deselect  
Writecyclesareinternallyself-timedandareinitiatedbythe  
risingedgeoftheclockinput.Writecyclescanbeonetofour  
bytes wide as controlled by the write control inputs.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• Power Supply  
Separate byte enables allow individual bytes to be written.  
The byte write operation is performed by using the byte  
write enable (BWE) input combined with one or more  
individual byte write signals (BWx). In addition, Global  
Write (GW) is available for writing all bytes at one time,  
regardless of the byte write controls.  
LPD: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VPD: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
• JEDEC 100-Pin TQFP and 165-pin PBGA  
package  
• Lead-free available  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
250  
2.6  
4
200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Rev. B  
02/03/06  
1234567...29

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与IS61VPD51236A-200B3相关器件

型号 品牌 获取价格 描述 数据表
IS61VPD51236A-200B3I ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-200TQ ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-200TQI ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-250B3 ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-250B3I ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-250TQ ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPD51236A-250TQI ISSI

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 		512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61VPS10018-166BI ISSI

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 		Cache SRAM, 1MX18, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61VPS10018-166TQ ISSI

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 		Cache SRAM, 1MX18, 3.5ns, CMOS, PQFP100, TQFP-100
IS61VPS10018-166TQI ISSI

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 		Cache SRAM, 1MX18, 3.5ns, CMOS, PQFP100, TQFP-100

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