5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> IS61VF25636A-7.5B3
IS61VF25636A-7.5B3 PDF预览

IS61VF25636A-7.5B3

更新时间： 2024-11-20 04:44:47
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器
页数 文件大小 规格书
32页 206K
描述
256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

阅读下载

中文翻译

获取价格

IS61VF25636A-7.5B3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：TBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
Is Samacsys：N最长访问时间：7.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：117 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：165字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.045 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.175 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

IS61VF25636A-7.5B3 数据手册

 浏览型号IS61VF25636A-7.5B3的Datasheet PDF文件第2页浏览型号IS61VF25636A-7.5B3的Datasheet PDF文件第3页浏览型号IS61VF25636A-7.5B3的Datasheet PDF文件第4页浏览型号IS61VF25636A-7.5B3的Datasheet PDF文件第5页浏览型号IS61VF25636A-7.5B3的Datasheet PDF文件第6页浏览型号IS61VF25636A-7.5B3的Datasheet PDF文件第7页 
®
IS61LF25636A IS61VF25636A  
IS61LF51218A IS61VF51218A  
ISSI  
256K x 36, 512K x 18  
9 Mb SYNCHRONOUS FLOW-THROUGH  
STATIC RAM  
MAY 2005  
DESCRIPTION  
FEATURES  
The ISSI IS61LF/VF25636A and IS61LF/VF51218A are  
high-speed, low-powersynchronousstaticRAMs designed  
to provide burstable, high-performance memory for commu-  
nication and networking applications. The IS61LF/  
VF25636A is organized as 262,144 words by 36 bits. The  
IS61LF/VF51218A is organized as 524,288 words by 18  
bits. Fabricated with ISSI's advanced CMOS technology,  
the device integrates a 2-bit burst counter, high-speed  
SRAM core, and high-drive capability outputs into a single  
monolithic circuit. All synchronous inputs pass through  
registers controlled by a positive-edge-triggered single  
clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
•
Three chip enable option for simple depth expan-  
sion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be one  
to four bytes wide as controlled by the write control inputs.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• Power Supply  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE) input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW) is  
available for writing all bytes at one time, regardless of the  
byte write controls.  
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VF: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address ad-  
vance) input pin.  
• JEDEC 100-Pin TQFP, 119-pin PBGA, and  
165-pin PBGA packages  
• Lead-free available  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-6.5  
6.5  
-7.5  
7.5  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
7.5  
8.5  
ns  
Frequency  
133  
117  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
1
05/04/05  
1234567...32

中文翻译

下载PDF

与IS61VF25636A-7.5B3相关器件

型号 品牌 获取价格 描述 数据表
IS61VF25636A-7.5B3I ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF25636A-7.5TQ ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF25636A-7.5TQI ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF25672A ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF25672A-6.5B1 ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF25672A-6.5B1I ISSI

获取价格

 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF409618B-6.5B2 ISSI

获取价格

 		2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF409618B-6.5B2L ISSI

获取价格

 		2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF409618B-6.5B3 ISSI

获取价格

 		2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF409618B-6.5B3L ISSI

获取价格

 		2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

与IS61VF25636A-7.5B3相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证