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IS61VF25636A-6.5B2 PDF预览

IS61VF25636A-6.5B2

更新时间: 2024-11-24 04:44:47
品牌 Logo 应用领域
美国芯成 - ISSI 内存集成电路静态存储器
页数 文件大小 规格书
32页 206K
描述
256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

IS61VF25636A-6.5B2 数据手册

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®
IS61LF25636A IS61VF25636A  
IS61LF51218A IS61VF51218A  
ISSI  
256K x 36, 512K x 18  
9 Mb SYNCHRONOUS FLOW-THROUGH  
STATIC RAM  
MAY 2005  
DESCRIPTION  
FEATURES  
The ISSI IS61LF/VF25636A and IS61LF/VF51218A are  
high-speed, low-powersynchronousstaticRAMs designed  
to provide burstable, high-performance memory for commu-  
nication and networking applications. The IS61LF/  
VF25636A is organized as 262,144 words by 36 bits. The  
IS61LF/VF51218A is organized as 524,288 words by 18  
bits. Fabricated with ISSI's advanced CMOS technology,  
the device integrates a 2-bit burst counter, high-speed  
SRAM core, and high-drive capability outputs into a single  
monolithic circuit. All synchronous inputs pass through  
registers controlled by a positive-edge-triggered single  
clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
Three chip enable option for simple depth expan-  
sion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be one  
to four bytes wide as controlled by the write control inputs.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• Power Supply  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE) input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW) is  
available for writing all bytes at one time, regardless of the  
byte write controls.  
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VF: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address ad-  
vance) input pin.  
• JEDEC 100-Pin TQFP, 119-pin PBGA, and  
165-pin PBGA packages  
• Lead-free available  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-6.5  
6.5  
-7.5  
7.5  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
7.5  
8.5  
ns  
Frequency  
133  
117  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
1
05/04/05  

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