Datasheet > IS61NLP51236

IS61NLP51236

更新时间： 2024-11-11 04:58:39

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
35页	278K
描述
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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数据手册

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IS61NLP51236 数据手册

IS61NLP25672/IS61NVP25672

IS61NLP51236/IS61NVP51236

IS61NLP102418/IS61NVP102418

ISSI

256K x 72, 512K x 36 and 1M x 18

18Mb, PIPELINE 'NO WAIT' STATE

BUS SRAM

JULY 2006

FEATURES

DESCRIPTION

The 18 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 256K words by 72 bits, 512K words

by 36 bits and 1M words by 18 bits, fabricated with ISSI's

advancedCMOStechnology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP, 165-ball PBGA and 209-

ball (x72) PBGA packages

• Power supply:

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

NVP: V^DD2.5V ( 5ꢀ), VDDQ 2.5V ( 5ꢀ)

NLP: V^DD3.3V ( 5ꢀ), VDDQ 3.3V/2.5V ( 5ꢀ)

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-250

2.6

-200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. G

07/10/06

12 3 4 5 6 7...35

中文翻译

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与IS61NLP51236相关器件

型号	品牌	获取价格	描述	数据表
IS61NLP51236-200B2I	ISSI	获取价格	ZBT SRAM, 512KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NLP51236-200B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200B3I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200B3LI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200TQ	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200TQI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200TQLI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-250B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-250B3I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-250B3LI	ISSI	获取价格	ZBT SRAM, 512KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, TFBGA-165

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