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IS61NLP51236B-200B3 PDF预览

IS61NLP51236B-200B3

更新时间： 2024-11-25 19:14:55
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
39页 1940K
描述
Standard SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, TFBGA-165

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中文翻译

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IS61NLP51236B-200B3 技术参数

生命周期：Active包装说明：TBGA,
Reach Compliance Code：unknown风险等级：5.71
最长访问时间：3 nsJESD-30 代码：R-PBGA-B165
长度：15 mm内存密度：18874368 bit
内存集成电路类型：STANDARD SRAM内存宽度：36
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX36
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM宽度：13 mm
Base Number Matches：1

IS61NLP51236B-200B3 数据手册

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IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B  
IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B  
512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS  
SYNCHRONOUS SRAM  
FEBRUARY 2014  
ADVANCED INFORMATION  
FEATURES  
DESCRIPTION  
•
•
•
•
•
•
100 percent bus utilization  
The 18Meg product family features high-speed,  
low-power synchronous static RAMs designed to  
provide a burstable, high-performance, 'no wait'  
state, device for networking and communications  
applications. They are organized as 512K words  
by 36 bits and 1024K words by 18 bits, fabricated  
with ISSI's advanced CMOS technology.  
Incorporating a 'no wait' state feature, wait cycles  
are eliminated when the bus switches from read  
to write, or write to read. This device integrates a  
2-bit burst counter, high-speed SRAM core, and  
high-drive capability outputs into a single  
monolithic circuit.  
All synchronous inputs pass through registers are  
controlled by a positive-edge-triggered single  
clock input. Operations may be suspended and all  
synchronous inputs ignored when Clock Enable,  
/CKE is HIGH. In this state the internal device will  
hold their previous values.  
No wait cycles between Read and Write  
Internal self-timed write cycle  
Individual Byte Write Control  
Single R/W (Read/Write) control pin  
Clock controlled, registered address, data and  
control  
Interleaved or linear burst sequence control  
using MODE input  
Three chip enables for simple depth  
expansion and address pipelining  
Power Down mode  
Common data inputs and data outputs  
/CKE pin to enable clock and suspend  
operation  
JEDEC 100-pin QFP, 165-ball BGA and 119-  
ball BGA packages  
•
•
•
•
•
•
•
Power supply:  
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
NVVP: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)  
JTAG Boundary Scan for BGA packages  
Commercial, Industrial and Automotive (x36)  
temperature support  
All Read, Write and Deselect cycles are initiated  
by the ADV input. When the ADV is HIGH the  
internal burst counter is incremented. New  
external addresses can be loaded when ADV is  
LOW.  
•
•
•
•
Lead-free available  
For leaded option, please contact ISSI.  
Write cycles are internally self-timed and are  
initiated by the rising edge of the clock inputs and  
when /WE is LOW. Separate byte enables allow  
individual bytes to be written.  
A burst mode pin (MODE) defines the order of the  
burst sequence. When tied HIGH, the interleaved  
burst sequence is selected. When tied LOW, the  
linear burst sequence is selected.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
Clock Access Time  
Cycle time  
-250  
2.6  
4
-200  
3.0  
5
Units  
ns  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at  
any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.  
Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders  
for products.  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. 00A  
1
2/13/2014  
1234567...39

中文翻译

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IS61NLP51236B-200TQLI ISSI

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 		IC SRAM 18M PARALLEL 100LQFP
IS61NLP51236B-200TQLI-TR ISSI

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 		IC SRAM 18M PARALLEL 100LQFP
IS61NLP51236B-250TQA3 ISSI

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 		512K X 36 STANDARD SRAM, 2.6ns, PQFP100, 14 X 20 MM, 1.40 MM, TQFP-100
IS61NLP6432A ISSI

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 		64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP6432A-200TQ ISSI

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 		64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP6432A-200TQI ISSI

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 		64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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