Datasheet > IS61NLP25618A-250TQI

IS61NLP25618A-250TQI

更新时间： 2024-11-25 04:58:39

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
29页	200K
描述
128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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IS61NLP12832A

IS61NLP12836A/IS61NVP12836A

IS61NLP25618A/IS61NVP25618A

128K x 32, 128K x 36, and 256K x 18

4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

ISSI

PRELIMINARYINFORMATION

SEPTEMBER 2005

FEATURES

DESCRIPTION

The 4 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organizedas128Kwordsby32bits,128Kwordsby36bits,

and256K wordsby18bits,fabricatedwithISSI'sadvanced

CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

• Power supply:

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

NVP: V^DD2.5V (± 5%), VDDQ 2.5V (± 5%)

NLP: V^DD3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

• Industrial temperature available

• Lead-free available

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-250

2.6

-200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00C

09/12/05

12 3 4 5 6 7...29

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与IS61NLP25618A-250TQI相关器件

型号	品牌	获取价格	描述	数据表
IS61NLP25618EC-200B2L	ISSI	获取价格	ZBT SRAM, 256KX18, 3.1ns, CMOS, PBGA119, BGA-119
IS61NLP25618EC-200B2LI	ISSI	获取价格	ZBT SRAM, 256KX18, 3.1ns, CMOS, PBGA119, BGA-119
IS61NLP25618EC-200TQLI	ISSI	获取价格	IC SRAM 4.5M PARALLEL 100TQFP
IS61NLP25618EC-200TQLI-TR	ISSI	获取价格	IC SRAM 4.5M PARALLEL 100TQFP
IS61NLP25618EC-250B2L	ISSI	获取价格	ZBT SRAM, 256KX18, 2.6ns, CMOS, PBGA119, BGA-119
IS61NLP25618EC-250B2LI	ISSI	获取价格	ZBT SRAM, 256KX18, 2.6ns, CMOS, PBGA119, BGA-119
IS61NLP25618EC-250B3L	ISSI	获取价格	ZBT SRAM, 256KX18, 2.6ns, CMOS, PBGA165, TFBGA-165
IS61NLP25632	ISSI	获取价格	256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM
IS61NLP25632-100B	ISSI	获取价格	ZBT SRAM, 256KX32, 5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61NLP25632-100BI	ISSI	获取价格	ZBT SRAM, 256KX32, 5ns, CMOS, PBGA119, PLASTIC, BGA-119

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