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IS61NLP25618EC-250B3L PDF预览

IS61NLP25618EC-250B3L

更新时间： 2024-11-25 19:51:51
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
40页 2686K
描述
ZBT SRAM, 256KX18, 2.6ns, CMOS, PBGA165, TFBGA-165

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中文翻译

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IS61NLP25618EC-250B3L 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：TBGA, BGA165,11X15,40
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.72最长访问时间：2.6 ns
最大时钟频率 (fCLK)：250 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.08 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.235 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：10宽度：13 mm
Base Number Matches：1

IS61NLP25618EC-250B3L 数据手册

 浏览型号IS61NLP25618EC-250B3L的Datasheet PDF文件第2页浏览型号IS61NLP25618EC-250B3L的Datasheet PDF文件第3页浏览型号IS61NLP25618EC-250B3L的Datasheet PDF文件第4页浏览型号IS61NLP25618EC-250B3L的Datasheet PDF文件第5页浏览型号IS61NLP25618EC-250B3L的Datasheet PDF文件第6页浏览型号IS61NLP25618EC-250B3L的Datasheet PDF文件第7页 
IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC  
IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC  
128K x36/32 and 256K x18 4Mb, ECC, PIPELINE 'NO WAIT' STATE  
BUS SYNCHRONOUS SRAM  
MAY 2013  
FEATURES  
DESCRIPTION  
•
•
•
•
•
•
100 percent bus utilization  
The 4Mb product family features high-speed, low-  
power synchronous static RAMs designed to  
provide a burstable, high-performance, 'no wait'  
state, device for networking and communications  
applications. They are organized as 128K words  
by 36 bits and 256K words by 18 bits, fabricated  
with ISSI's advanced CMOS technology.  
Incorporating a 'no wait' state feature, wait cycles  
are eliminated when the bus switches from read  
to write, or write to read. This device integrates a  
2-bit burst counter, high-speed SRAM core, and  
high-drive capability outputs into a single  
monolithic circuit.  
All synchronous inputs pass through registers are  
controlled by a positive-edge-triggered single  
clock input. Operations may be suspended and all  
synchronous inputs ignored when Clock Enable,  
/CKE is HIGH. In this state the internal device will  
hold their previous values.  
All Read, Write and Deselect cycles are initiated  
by the ADV input. When the ADV is HIGH the  
internal burst counter is incremented. New  
external addresses can be loaded when ADV is  
LOW.  
Write cycles are internally self-timed and are  
initiated by the rising edge of the clock inputs and  
when /WE is LOW. Separate byte enables allow  
individual bytes to be written.  
No wait cycles between Read and Write  
Internal self-timed write cycle  
Individual Byte Write Control  
Single R/W (Read/Write) control pin  
Clock controlled, registered address, data and  
control  
•
•
Interleaved or linear burst sequence control  
using MODE input  
Three chip enables for simple depth  
expansion and address pipelining  
Power Down mode  
•
•
•
Common data inputs and data outputs  
/CKE pin to enable clock and suspend  
operation  
•
•
JEDEC 100-pin TQFP, 165-ball PBGA and  
119-ball PBGA packages  
Power supply:  
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
JTAG Boundary Scan for PBGA packages  
Industrial and Automotive temperature support  
Lead-free available  
•
•
•
•
A burst mode pin (MODE) defines the order of the  
burst sequence. When tied HIGH, the interleaved  
burst sequence is selected. When tied LOW, the  
linear burst sequence is selected  
Error Detection and Error Correction  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
Clock Access Time  
Cycle time  
250  
2.6  
4
200  
3.1  
5
Units  
ns  
tKC  
ns  
fMAX  
Frequency  
250  
200  
MHz  
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. B  
1
05/03/2013  
1234567...40

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IS61NLP25632-100B ISSI

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 		ZBT SRAM, 256KX32, 5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61NLP25632-100BI ISSI

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IS61NLP25632-100TQ ISSI

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 		ZBT SRAM, 256KX32, 5ns, CMOS, PQFP100, TQFP-100
IS61NLP25632-133TQI ISSI

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IS61NLP25632-5TQ ISSI

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 		ZBT SRAM, 256KX32, 5ns, CMOS, PQFP100, TQFP-100
IS61NLP25636 ISSI

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 		256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM
IS61NLP25636-133TQI ISSI

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 		ZBT SRAM, 256KX36, 4.2ns, CMOS, PQFP100, TQFP-100
IS61NLP25636A ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP25636A-200B2 ISSI

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 		256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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