IS61NLF25672-7.5B1

更新时间： 2024-11-09 12:58:35

品牌	Logo	应用领域
美国芯成 - ISSI		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
35页	251K
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IS61NLF25672/IS61NVF25672

IS61NLF51236/IS61NVF51236

IS61NLF102418/IS61NVF102418

ISSI

AUGUST 2005

256K x 72, 512K x 36 and 1M x 18

18Mb, FLOW THROUGH 'NO WAIT'

STATE BUS SRAM

FEATURES

DESCRIPTION

The 18 Meg 'NLF/NVF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 256K words by 72 bits, 512K words

by 36 bits and 1M words by 18 bits, fabricated with ISSI's

advancedCMOStechnology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP, 165-ball PBGA and 209-

ball (x72) PBGA packages

• Power supply:

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

NVF: V^DD2.5V (± 5%), VDDQ 2.5V (± 5%)

NLF: V^DD3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

6.5

7.5

133

7.5

8.5

117

Units

Clock Access Time

Cycle Time

tKC

Frequency

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. B

08/26/05

12 3 4 5 6 7...35

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与IS61NLF25672-7.5B1相关器件

型号	品牌	获取价格	描述	数据表
IS61NLF25672-7.5B1I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25672-7.5B1I-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 209LFBGA
IS61NLF409618B	ISSI	获取价格	100 percent bus utilization
IS61NLF51218	ISSI	获取价格	SRAM
IS61NLF51218-9TQ	ISSI	获取价格	ZBT SRAM, 512KX18, 9ns, CMOS, PQFP100, TQFP-100
IS61NLF51218A	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5B2	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5B2I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5B3	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF51218A-6.5B3I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

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