Datasheet > IS61NLF25636A

IS61NLF25636A

更新时间： 2024-11-09 05:39:35

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
37页	236K
描述
256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS61NLF25636A 数据手册

IS61NLF25636A/IS61NVF25636A

IS61NLF51218A/IS61NVF51218A

ISSI

256K x 36 and 512K x 18

9Mb, FLOW THROUGH 'NO WAIT'

STATE BUS SRAM

AUGUST 2005

FEATURES

DESCRIPTION

The 9 Meg 'NLF/NVF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 256K words by 36 bits and 512K words by 18

bits, fabricated with ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single Read/Write control pin

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-

ball PBGA packages

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

• Power supply:

NVF: V^DD2.5V (± 5%), VDDQ 2.5V (± 5%)

NLF: V^DD3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

tKQ

Parameter

6.5

7.5

133

7.5

8.5

117

Units

Clock Access Time

Cycle Time

tKC

Frequency

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. B

08/26/05

12 3 4 5 6 7...37

中文翻译

下载PDF

与IS61NLF25636A相关器件

型号	品牌	获取价格	描述	数据表
IS61NLF25636A-6.5B2	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25636A-6.5B2I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25636A-6.5B3	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25636A-6.5B3I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25636A-6.5TQ	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25636A-6.5TQI	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25636A-7.5B2	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25636A-7.5B2I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25636A-7.5B3	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF25636A-7.5B3I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

与IS61NLF25636A相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

47
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NLF25636A

IS61NLF25636A 数据手册

与IS61NLF25636A相关器件

与IS61NLF25636A相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NLF25636A

IS61NLF25636A 数据手册

与IS61NLF25636A相关器件

与IS61NLF25636A相关文章

您还可以找

您在本页遇到什么问题？