Datasheet > IS61NF12836

IS61NF12836

更新时间： 2024-11-18 00:04:27

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
20页	136K
描述
128K32,128K36 AND 256K*18 FLOW-THROUGH 'NO WAIT' STATE BUS SRAM

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IS61NF12836 数据手册

IS61NF12832 IS61NF12836 IS61NF25618

IS61NLF12832 IS61NLF12836 IS61NLF25618 ISSI

128K x 32, 128K x 36 and 256K x 18

FLOW-THROUGH 'NO WAIT' STATE BUS

SRAM

PRELIMINARY INFORMATION

MAY 2002

FEATURES

DESCRIPTION

The 4 Meg 'NF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 131,072 words by 32 bits, 131,072 words

by 36 bits and 262,144 words by 18 bits, fabricated with

ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining for TQFP

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 119 PBGA package

• Single +3.3V power supply (± 5%)

• NF Version: 3.3V I/O Supply Voltage

• NLF Version: 2.5V I/O Supply Voltage

• Industrialtemperatureavailable

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-8.5*

8.5

-9

-10

Units

Clock Access Time

Cycle Time

tKC

Frequency

100

MHz

*This speed available only in NF version

ISSIreservestherighttomakechangesthisspecificationhereinanditproductsatanytimewithoutnotice. ISSIassumesnoresponsibilityorliabilityarisingoutoftheapplicationoruseofanyinformation,

productorservicesdescribedherein.Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

PRELIMINARYINFORMATION Rev.00E

05/29/02

12 3 4 5 6 7...20

中文翻译

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与IS61NF12836相关器件

型号	品牌	获取价格	描述	数据表
IS61NF12836-10B	ISSI	获取价格	ZBT SRAM, 128KX36, 10ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61NF12836-10BI	ISSI	获取价格	128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM
IS61NF12836-10TQ	ISSI	获取价格	128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM
IS61NF12836-10TQI	ISSI	获取价格	128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM
IS61NF12836-8.5B	ISSI	获取价格	128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM
IS61NF12836-8.5TQ	ISSI	获取价格	128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM
IS61NF12836-9B	ISSI	获取价格	ZBT SRAM, 128KX36, 9ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61NF25618	ISSI	获取价格	128K32,128K36 AND 256K*18 FLOW-THROUGH 'NO WAIT' STATE BUS SRAM
IS61NF25618-10B	ISSI	获取价格	ZBT SRAM, 256KX18, 10ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61NF25618-10BI	ISSI	获取价格	128K x 32, 128K x 36 and 256K x 18 FLOW-THROUGH NO WAIT STATE BUS SRAM

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