Datasheet > IS61NF51218-8.5TQ

IS61NF51218-8.5TQ

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
20页	154K
描述
ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, TQFP-100

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IS61NF25632 IS61NF25636 IS61NF51218

IS61NLF25632 IS61NLF25636 IS61NLF51218 ISSI

256K x 32, 256K x 36 and 512K x 18

FLOW-THROUGH 'NO WAIT' STATE BUS

SRAM

PRELIMINARY INFORMATION

SEPTEMBER2000

FEATURES

DESCRIPTION

The 8 Meg 'NF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 262,144 words by 32 bits, 262,144 words

by 36 bits and 524,288 words by 18 bits, fabricated with

ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining for TQFP

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 119 PBGA package

• Single +3.3V power supply (± 5%)

• NF Version: 3.3V I/O Supply Voltage

• NLF Version: 2.5V I/O Supply Voltage

• Industrialtemperatureavailable

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-8.5*

8.5

-9

-10

Units

Clock Access Time

Cycle Time

tKC

Frequency

100

MHz

*This speed available only in NF version

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00C

11/30/00

12 3 4 5 6 7...20

中文翻译

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与IS61NF51218-8.5TQ相关器件

型号	品牌	获取价格	描述	数据表
IS61NLF102418	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF102418-6.5B2	ISSI	获取价格	ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IS61NLF102418-6.5B2I	ISSI	获取价格	ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IS61NLF102418-6.5B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF102418-6.5B3I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF102418-6.5B3I-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 165TFBGA
IS61NLF102418-6.5B3-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 165TFBGA
IS61NLF102418-6.5TQ	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF102418-6.5TQI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
IS61NLF102418-6.5TQ-TR	ISSI	获取价格	IC SRAM 18M PARALLEL 100TQFP

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