IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
NOVEMBER 2013
256K x 72, 512K x 36 and 1M x 18
18Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
FEATURES
DESCRIPTION
Theꢀ18ꢀMegꢀ'NLF/NVF'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ
aꢀ burstable,ꢀ high-performance,ꢀ 'noꢀ wait'ꢀ state,ꢀ deviceꢀ
forꢀ networkingꢀ andꢀ communicationsꢀ applications.ꢀ Theyꢀ
areꢀ organizedꢀ asꢀ 256Kꢀ wordsꢀ byꢀ 72ꢀ bits,ꢀ 512Kꢀ wordsꢀ
byꢀ36ꢀbitsꢀandꢀ1Mꢀꢀwordsꢀbyꢀ18ꢀbits,ꢀfabricatedꢀwithꢀISSI'sꢀ
advanced CMOS technology.
•ꢀ 100ꢀpercentꢀbusꢀutilization
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite
•ꢀ Internalꢀself-timedꢀwriteꢀcycle
•ꢀ IndividualꢀByteꢀWriteꢀControl
•ꢀ SingleꢀRead/Writeꢀcontrolꢀpin
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ
ꢀ
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ
eliminated when the bus switches from read to write, or
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ
into a single monolithic circuit.
data and control
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-
ing MODE input
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ
Allsynchronousinputspassthroughregistersarecontrolled
byapositive-edge-triggeredsingleclockinput.Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ
device will hold their previous values.
and address pipelining
•ꢀ PowerꢀDownꢀmode
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs
•ꢀ CKE pin to enable clock and suspend operation
AllꢀRead,ꢀWriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ
isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ
whenꢀADVꢀisꢀLOW.
•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ209-
ballꢀ(x72)ꢀPBGAꢀpackages
•ꢀ Powerꢀsupply:
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ
the rising edge of the clock inputs and when WEꢀisꢀLOW.ꢀ
Separate byte enables allow individual bytes to be written.
NVF:ꢀVdd 2.5Vꢀ(±ꢀ5%),ꢀVddqꢀ2.5Vꢀ(±ꢀ5%)
NLF:ꢀVddꢀ3.3Vꢀ(±ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ(±ꢀ5%)
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages
•ꢀ Industrialꢀtemperatureꢀavailable
•ꢀ Lead-freeꢀavailable
A burst mode pin (MODE) defines the order of the burst
sequence.ꢀWhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ
selected.
FAST ACCESS TIME
Symbol
Parameter
6.5
7.5
Units
ns
tkqꢀ
tkcꢀ
ꢀ
ClockꢀAccessꢀTimeꢀ
CycleꢀTimeꢀ
6.5ꢀ
7.5ꢀ
133ꢀ
7.5ꢀ
8.5ꢀ
117ꢀ
ns
ꢀ
Frequencyꢀ
MHz
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil-
ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. E
10/25/2013
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