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IS61NLF102418-6.5B2 PDF预览

IS61NLF102418-6.5B2

更新时间： 2024-02-19 17:30:11
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
40页 279K
描述
ZBT SRAM, 1MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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IS61NLF102418-6.5B2 技术参数

是否Rohs认证： 不符合生命周期：Active
零件包装代码：BGA包装说明：BGA,
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.48最长访问时间：6.5 ns
其他特性：FLOW-THROUGH ARCHITECTUREJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：18874368 bit内存集成电路类型：ZBT SRAM
内存宽度：18功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX18封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：2.41 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
宽度：14 mmBase Number Matches：1

IS61NLF102418-6.5B2 数据手册

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IS61NLF25672/IS61NVF25672  
IS61NLF51236/IS61NVF51236  
IS61NLF102418/IS61NVF102418  
®
ISSI  
ADVANCE INFORMATION  
AUGUST 2003  
256K x 72, 512K x 36 and 1M x 18  
18Mb, FLOW THROUGH 'NO WAIT'  
STATE BUS SRAM  
FEATURES  
DESCRIPTION  
The 18 Meg 'NLF/NVF' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
networking and communications applications. They are  
organized as 256K words by 72 bits, 512K words  
by 36 bits and 1M words by 18 bits, fabricated with ISSI's  
advancedCMOStechnology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single Read/Write control pin  
• Clock controlled, registered address,  
data and control  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Interleaved or linear burst sequence control using  
MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
• JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball  
PBGA and 209-ball (x72) PBGA packages  
• Power supply:  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be written.  
NVF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
NLF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
• JTAG Boundary Scan for PBGA packages  
• Industrial temperature available  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
6.5  
6.5  
7.5  
133  
7.5  
7.5  
8.5  
117  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
MHz  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. 00B  
1
08/19/03  
1234567...40

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IS61NLF102418-7.5B2 ISSI

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IS61NLF102418-7.5B2I ISSI

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 		ZBT SRAM, 1MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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