Datasheet > IS61LV6464-8TQ

IS61LV6464-8TQ

更新时间： 2024-11-17 23:59:47

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器时钟
页数	文件大小	规格书
17页	125K
描述
x64 Fast Synchronous SRAM

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IS61LV6464-8TQ 数据手册

IS61LV6464

ISSI

APRIL 2001

64K x 64 SYNCHRONOUS

PIPELINE STATIC RAM

FEATURES

DESCRIPTION

The ISSI IS61LV6464 is a high-speed, low-power synchro-

nous static RAM designed to provide a burstable, high-

performance, secondary cache for the Pentium™, 680X0™,

and PowerPC™ microprocessors. It is organized as 65,536

words by 64 bits, fabricated with ISSI's advanced CMOS

technology. The device integrates a 2-bit burst counter, high-

speed SRAM core, and high-drive capability outputs into a

single monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single clock

input.

• Fast access time:

– -100 MHz; 6 ns-83 MHz;

7 ns-75 MHz; 8 ns-66 MHz

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

eight bytes wide as controlled by the write control inputs.

• Five chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 128-Pin TQFP 14mm x 20mm

package

Separate byte enables allow individual bytes to be written.

BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 con-

trols I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls

I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-

I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being

LOW. A LOW on GW input would cause all bytes to be written.

• Single +3.3V power supply

• 2.5V V^CCQ(I/O supply)

• Control pins mode upon power-up:

– MODE in interleave burst mode

– ZZ in normal operation mode

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated inter-

nally by the IS61LV6464 and controlled by the ADV (burst

address advance) input pin.

These control pins can be connected to GNDQ

or VCCQ to alter their power-up state

Asynchronoussignalsincludeoutputenable(OE),sleepmode

input(ZZ), andburstmodeinput(MODE). AHIGHinputonthe

ZZ pin puts the SRAM in the power-down state. When ZZ is

pulled LOW (or no connect), the SRAM normally operates

after the wake-up period. A LOW input, i.e., GND^Q, on MODE

pin selects LINEAR Burst. A VCCQ (or no connect) on MODE

pin selects INTERLEAVED Burst.

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

12 3 4 5 6 7...17

中文翻译

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与IS61LV6464-8TQ相关器件

型号	品牌	获取价格	描述	数据表
IS61LV6464-8TQI	ETC	获取价格	x64 Fast Synchronous SRAM
IS61M256-10J	ETC	获取价格	x8 SRAM
IS61M256-10N	ETC	获取价格	x8 SRAM
IS61M256-12J	ETC	获取价格	x8 SRAM
IS61M256-12N	ETC	获取价格	x8 SRAM
IS61M256-15J	ETC	获取价格	x8 SRAM
IS61M256-15N	ETC	获取价格	x8 SRAM
IS61M256-20J	ETC	获取价格	x8 SRAM
IS61M256-20N	ETC	获取价格	x8 SRAM
IS61M256-25J	ETC	获取价格	x8 SRAM

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