Datasheet > IS61LV6464-8TQI

IS61LV6464-8TQI

更新时间： 2024-02-25 02:10:46

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器时钟
页数	文件大小	规格书
17页	125K
描述
x64 Fast Synchronous SRAM

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IS61LV6464-8TQI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, TQFP-128
针数：	128	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.88	Is Samacsys：	N
最长访问时间：	8 ns	其他特性：	SELF-TIMED WRITE; BURST COUNTER; BYTE WRITE; LINEAR/INTERLEAVED BURST SEQUENCE
最大时钟频率 (fCLK)：	66 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G128	JESD-609代码：	e0
长度：	20 mm	内存密度：	4194304 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	64
功能数量：	1	端子数量：	128
字数：	65536 words	字数代码：	64000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	64KX64
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP128,.63X.87,20
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.01 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.17 mA	最大供电电压 (Vsup)：	3.63 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

IS61LV6464-8TQI 数据手册

IS61LV6464

ISSI

APRIL 2001

64K x 64 SYNCHRONOUS

PIPELINE STATIC RAM

FEATURES

DESCRIPTION

The ISSI IS61LV6464 is a high-speed, low-power synchro-

nous static RAM designed to provide a burstable, high-

performance, secondary cache for the Pentium™, 680X0™,

and PowerPC™ microprocessors. It is organized as 65,536

words by 64 bits, fabricated with ISSI's advanced CMOS

technology. The device integrates a 2-bit burst counter, high-

speed SRAM core, and high-drive capability outputs into a

single monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single clock

input.

• Fast access time:

– -100 MHz; 6 ns-83 MHz;

7 ns-75 MHz; 8 ns-66 MHz

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

eight bytes wide as controlled by the write control inputs.

• Five chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 128-Pin TQFP 14mm x 20mm

package

Separate byte enables allow individual bytes to be written.

BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 con-

trols I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls

I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-

I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being

LOW. A LOW on GW input would cause all bytes to be written.

• Single +3.3V power supply

• 2.5V V^CCQ(I/O supply)

• Control pins mode upon power-up:

– MODE in interleave burst mode

– ZZ in normal operation mode

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated inter-

nally by the IS61LV6464 and controlled by the ADV (burst

address advance) input pin.

These control pins can be connected to GNDQ

or VCCQ to alter their power-up state

Asynchronoussignalsincludeoutputenable(OE),sleepmode

input(ZZ), andburstmodeinput(MODE). AHIGHinputonthe

ZZ pin puts the SRAM in the power-down state. When ZZ is

pulled LOW (or no connect), the SRAM normally operates

after the wake-up period. A LOW input, i.e., GND^Q, on MODE

pin selects LINEAR Burst. A VCCQ (or no connect) on MODE

pin selects INTERLEAVED Burst.

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

12 3 4 5 6 7...17

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