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IS61LV51216-8TL PDF预览

IS61LV51216-8TL

更新时间: 2024-01-20 21:33:17
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
15页 117K
描述
512K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV51216-8TL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2,针数:44
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.88
最长访问时间:8 nsJESD-30 代码:R-PDSO-G44
JESD-609代码:e0长度:18.415 mm
内存密度:8388608 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:44
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

IS61LV51216-8TL 数据手册

 浏览型号IS61LV51216-8TL的Datasheet PDF文件第2页浏览型号IS61LV51216-8TL的Datasheet PDF文件第3页浏览型号IS61LV51216-8TL的Datasheet PDF文件第4页浏览型号IS61LV51216-8TL的Datasheet PDF文件第5页浏览型号IS61LV51216-8TL的Datasheet PDF文件第6页浏览型号IS61LV51216-8TL的Datasheet PDF文件第7页 
®
IS61LV51216  
IS64LV51216  
ISSI  
512K x 16 HIGH SPEED ASYNCHRONOUS  
CMOS STATIC RAM WITH 3.3V SUPPLY  
DECEMBER2005  
FEATURES  
DESCRIPTION  
The ISSI IS61/64LV51216 is a high-speed, 8M-bit static  
RAMorganizedas525,288wordsby16bits.Itisfabricated  
using ISSI's high-performance CMOS technology. This  
highly reliable process coupled with innovative circuit de-  
sign techniques, yields high-performance and low power  
consumption devices.  
• High-speed access time:  
— 8, 10, and 12 ns  
• CMOS low power operation  
• Low stand-by power:  
— Less than 5 mA (typ.) CMOS stand-by  
• TTL compatible interface levels  
• Single 3.3V power supply  
When CE is HIGH (deselected), the device assumes a  
standby mode at which the power dissipation can be  
reduced down with CMOS input levels.  
• Fully static operation: no clock or refresh  
required  
Easy memory expansion is provided by using Chip Enable  
and Output Enable inputs, CE and OE. The active LOW  
Write Enable (WE) controls both writing and reading of the  
memory. A data byte allows Upper Byte (UB) and Lower  
Byte (LB) access.  
• Three state outputs  
• Data control for upper and lower bytes  
• Industrial and Automotive temperatures available  
• Lead-free available  
The IS61/64LV51216 is packaged in the JEDEC standard  
44-pin TSOP Type II and 48-pin Mini BGA (9mm x 11mm).  
FUNCTIONAL BLOCK DIAGRAM  
512K x 16  
MEMORY ARRAY  
A0-A18  
DECODER  
VDD  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. D  
12/06/05  

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