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IS61LF6432A-8.5TQLI PDF预览

IS61LF6432A-8.5TQLI

更新时间： 2024-11-11 04:58:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
16页 91K
描述
64K x 32, 64Kx36 SYNCHRONOUS FLOW-THROUGH STATIC RAM

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IS61LF6432A-8.5TQLI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.67
Is Samacsys：N最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：90 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：2097152 bit内存集成电路类型：CACHE SRAM
内存宽度：32湿度敏感等级：3
功能数量：1端子数量：100
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.035 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.15 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：14 mmBase Number Matches：1

IS61LF6432A-8.5TQLI 数据手册

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®
IS61LF6436A  
IS61LF6432A  
ISSI  
64K x 32, 64Kx36  
SYNCHRONOUS FLOW-THROUGH  
STATIC RAM  
OCTOBER2005  
DESCRIPTION  
FEATURES  
TheISSIIS61LF6432AandIS61LF6436Aarehigh-speed,  
low-power synchronous static RAM designed to provide a  
burstable, high-performance, memory. IS61LF6432A is  
organized as 65,536 words by 32 bits. IS61LF6436A is  
organized as 65,536 words by 36 bits. They are fabricated  
with ISSI's advanced CMOS technology. The device inte-  
grates a 2-bit burst counter, high-speed SRAM core, and  
high-drivecapabilityoutputsintoasinglemonolithiccircuit.  
All synchronous inputs pass through registers controlled  
by a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Interleaved or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
• Power-down control by ZZ input  
• JEDEC 100-Pin TQFP package  
• Power Supply:  
Writecyclesareinternallyself-timedandareinitiatedbythe  
risingedgeoftheclockinput. Writecyclescanbefromone  
to four bytes wide as controlled by the write control inputs.  
Separate byte enables allow individual bytes to be written.  
BWacontrolsDQa,BWbcontrolsDQb,BWccontrolsDQc,  
BWd controls DQd, conditioned by BWE being LOW. A  
LOW on GW input would cause all bytes to be written.  
+3.3V VDD  
+3.3V or 2.5V VDDQ  
• Control pins mode upon power-up:  
– MODE in interleave burst mode  
– ZZ in normal operation mode  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally by the IS61LF6432A/36A and controlled by the  
ADV (burst address advance) input pin.  
• Industrial Temperature Available:  
(-40oC to +85oC)  
• Lead-free available  
The mode pin is used to select the burst sequence order.  
Linear burst is achieved when this pin is tied LOW. Inter-  
leave burst is achieved when this pin is tied HIGH or left  
floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
8.5  
8.5  
11  
Unit  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
90  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. B  
1
08/25/05  
1234567...16

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