Datasheet > IS61LPD102418-250B3I

IS61LPD102418-250B3I

更新时间： 2024-11-12 10:12:39

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
29页	159K
描述
Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165

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IS61VPD51236A IS61VPD102418A

IS61LPD51236A IS61LPD102418A

ISSI

512K x 36, 1024K x 18

18Mb SYNCHRONOUS PIPELINED,

DOUBLE CYCLE DESELECT STATIC RAM

ADVANCE INFORMATION

DECEMBER 2002

DESCRIPTION

FEATURES

The ISSI IS61LPD/VPD51236A and IS61LPD/

VPD102418A are high-speed, low-power synchronous

static RAMs designed to provide burstable, high-performance

memory for communication and networking applications.

TheIS61LPD/VPD51236Aisorganizedas524,288words

by 36 bits, and the IS61LPD/VPD102418A is organized as

1,048,576 words by 18 bits. Fabricated with ISSI's ad-

vanced CMOS technology, the device integrates a 2-bit

burst counter, high-speed SRAM core, and high-drive

capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Double cycle deselect

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). In addition, Global

Write (GW) is available for writing all bytes at one time,

regardless of the byte write controls.

LPD: V^DD3.3V + 5%, VDDQ 3.3V/2.5V + 5%

VPD: V^DD2.5V + 5%, VDDQ 2.5V + 5%

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address

advance) input pin.

• JEDEC 100-Pin TQFP,

119-pin PBGA, and 165-pin PBGA package

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

250

2.6

200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCEINFORMATION Rev. 00A

12/17/02

12 3 4 5 6 7...29

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与IS61LPD102418-250B3I相关器件

型号	品牌	获取价格	描述	数据表
IS61LPD102418-250TQ	ISSI	获取价格	Cache SRAM, 1MX18, 2.6ns, CMOS, PQFP100, TQFP-100
IS61LPD102418-250TQI	ISSI	获取价格	Cache SRAM, 1MX18, 2.6ns, CMOS, PQFP100, TQFP-100
IS61LPD102418A	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD102418A-200B3	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD102418A-200B3I	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD102418A-200TQ	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD102418A-200TQI	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD102418A-250B3	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD102418A-250B3I	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD102418A-250TQ	ISSI	获取价格	512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

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