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IS61DDPB24M18-400M3L PDF预览

IS61DDPB24M18-400M3L

更新时间： 2024-11-21 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器双倍数据速率
页数 文件大小 规格书
24页 606K
描述
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs

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中文翻译

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IS61DDPB24M18-400M3L 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：0.45 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：400 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：17 mm内存密度：75497472 bit
内存集成电路类型：DDR SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：4MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.7 mm
最大待机电流：0.2 A最小待机电流：1.7 V
子类别：SRAMs最大压摆率：0.55 mA
最大供电电压 (Vsup)：1.89 V最小供电电压 (Vsup)：1.71 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：10宽度：15 mm

IS61DDPB24M18-400M3L 数据手册

 浏览型号IS61DDPB24M18-400M3L的Datasheet PDF文件第2页浏览型号IS61DDPB24M18-400M3L的Datasheet PDF文件第3页浏览型号IS61DDPB24M18-400M3L的Datasheet PDF文件第4页浏览型号IS61DDPB24M18-400M3L的Datasheet PDF文件第5页浏览型号IS61DDPB24M18-400M3L的Datasheet PDF文件第6页浏览型号IS61DDPB24M18-400M3L的Datasheet PDF文件第7页 
72 Mb (2M x 36 & 4M x 18)  
.
DDR-IIP (Burst of 2) CIO Synchronous SRAMs  
(2.5 Cycle Read Latency)  
Advanced Information  
May 2009  
Two echo clocks (CQ and CQ) that are delivered  
simultaneously with data.  
•
•
Features  
• 2M x 36 or 4M x 18.  
+1.8V core power supply and 1.5, 1.8V VDDQ  
used with 0.75, 0.9V VREF  
,
•
On-chip delay-locked loop (DLL) for wide data  
valid window.  
.
•
•
HSTL input and output levels.  
• Common data input/output bus.  
Registered addresses, write and read controls,  
byte writes, data in, and data outputs.  
•
Synchronous pipeline read with self-timed late  
write operation.  
• Full data coherency.  
•
Double data rate (DDR-IIP) interface for read and  
•
Boundary scan using limited set of JTAG 1149.1  
functions.  
write input ports.  
•
•
Fixed 2-bit burst for read and write operations.  
Clock stop support.  
•
•
Byte write capability.  
Fine ball grid array (FBGA) package  
- 15mm x 17mm body size  
- 1mm pitch  
• Two input clocks (K and K) for address and con-  
trol registering at rising edges only.  
Industrial temperature available upon request.  
•
- 165-ball (11 x 15) array  
•
Programmable impedance output drivers via 5x  
user-supplied precision resistor.  
Description  
The 72Mb IS61DDPB22M36 and  
The following are registered on the rising edge of  
the K clock:  
IS61DDPB24M18 are synchronous, high-perfor-  
mance CMOS static random access memory  
(SRAM) devices. These SRAMs have a common I/O  
bus. The rising edge of K clock initiates the  
read/write operation, and all internal operations are  
self-timed.  
•
y
B te writes  
• Data-in for second burst addresses  
Data-out  
•
Byte writes can change with the corresponding data-  
in to enable or disable writes on a per-byte basis. An  
internal write buffer enables the data-ins to be regis-  
tered one cycle later than the write address. The first  
data-in burst is clocked with the rising edge of the  
next K clock, and the second burst is timed to the  
following rising edge of the K clock.  
Refer to the Timing Reference Diagram for Truth  
Table on page 8 for a description of the basic opera-  
tions of these DDR-IIP (Burst of 2) CIO SRAMs.  
The input addresses are registered on all rising  
edges of the K clock. The DQ bus operates at  
double data rate for reads and writes. The following  
are registered internally on the rising edge of the K  
clock:  
During the burst read operation, at the first burst the  
data-outs are updated from output registers off the  
second rising edge of the K clock (2.5 cycles later).  
At the second burst, the data-outs are updated with  
the fourth rising edge of the corresponding K clock  
(see page 8).  
•
•
•
Read and write addresses  
Address load  
Read/write enable  
y
B te writes  
Data-in  
Data-out  
•
•
The device is operated with a single +1.8V power  
supply and is compatible with HSTL I/O interfaces.  
Integrated Silicon Solution, Inc.  
1
Rev. 00A  
03/31/08  
1234567...24

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与IS61DDPB24M18-400M3L相关器件

型号 品牌 获取价格 描述 数据表
IS61DDPB24M18A ISSI

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 		4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB24M18A/A1/A2 ISSI

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 		4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB24M18A1-550M3I ISSI

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 		DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, LFBGA-165
IS61DDPB24M18A1-550M3L ISSI

获取价格

 		DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDPB24M18A1-550M3LI ISSI

获取价格

 		DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDPB24M18A2-550M3I ISSI

获取价格

 		DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, LFBGA-165
IS61DDPB24M18A2-550M3LI ISSI

获取价格

 		DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, LEAD FREE, LFBGA-165
IS61DDPB24M18B ISSI

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 		Fixed 2-bit burst for read and write operations
IS61DDPB24M18B1 ISSI

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 		Fixed 2-bit burst for read and write operations
IS61DDPB24M18B2 ISSI

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 		Fixed 2-bit burst for read and write operations

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