IS61DDPB21M18A/A1/A2
IS61DDPB251236A/A1/A2
1Mx18, 512Kx36
ADVANCED INFORMATION
JULY 2012
18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
FEATURES
DESCRIPTION
The 18Mb IS61DDPB251236A/A1/A2 and
512Kx36 and 1Mx18 configuration available.
IS61DDPB21M18A/A1/A2 are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have a common I/O bus. The rising
edge of K clock initiates the read/write operation, and all
internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the
basic operations of these DDR-IIP (Burst of 2) CIO SRAMs.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write
operation.
Double Data Rate (DDR) interface for read and
write input ports.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate.
2.5 cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
The following are registered internally on the rising edge of
the K clock:
Two input clocks (K and K#) for address and control
registering at rising edges only.
Read/write address
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
Read enable
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
Write enable
Byte writes
HSTL input and output interface.
Data-in for first burst addresses
Data-Out for second burst addresses
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
The following are registered on the rising edge of the K#
clock:
Full data coherency.
Byte writes
Boundary scan using limited set of JTAG 1149.1
functions.
Data-in for second burst addresses
Data-Out for first burst addresses
Byte write capability.
Fine ball grid array (FBGA) package:
13mm x 15mm & 15mm x 17mm body size
165-ball (11 x 15) array
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock.
Programmable impedance output drivers via 5x
user-supplied precision resistor.
Data Valid Pin (QVLD).
ODT (On Die Termination) feature is supported
optionally on data input, K/K#, and BWx#.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the third rising
edge of the K# clock (starting two and half cycles later after
read command). The data-outs from the second burst are
updated with the fourth rising edge of the K clock where read
command receives at the first rising edge of K.
The end of top mark (A/A1/A2) is to define options.
IS61DDPB251236A : Don’t care ODT function
and pin connection
IS61DDPB251236A1 : Option1
IS61DDPB251236A2 : Option2
Refer to more detail description at page 6 for each
ODT option.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
1
7/05/2012
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