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IS43DR81280B-3DBI-TR PDF预览

IS43DR81280B-3DBI-TR

更新时间： 2024-11-24 22:59:27
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美国芯成 - ISSI 动态存储器
页数 文件大小 规格书
29页 1060K
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IC DRAM 1G PARALLEL 60TWBGA

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IS43DR81280B-3DBI-TR 数据手册

 浏览型号IS43DR81280B-3DBI-TR的Datasheet PDF文件第2页浏览型号IS43DR81280B-3DBI-TR的Datasheet PDF文件第3页浏览型号IS43DR81280B-3DBI-TR的Datasheet PDF文件第4页浏览型号IS43DR81280B-3DBI-TR的Datasheet PDF文件第5页浏览型号IS43DR81280B-3DBI-TR的Datasheet PDF文件第6页浏览型号IS43DR81280B-3DBI-TR的Datasheet PDF文件第7页 
IS43/46DR81280B(L), IS43/46DR16640B(L)  
MARCH 2015  
1Gb (x8, x16) DDR2 SDRAM  
FEATURES  
Clock frequency up to 400MHz  
8 internal banks for concurrent operation  
4-bit prefetch architecture  
Programmable CAS Latency: 3, 4, 5, 6 and 7  
Programmable Additive Latency: 0, 1, 2, 3, 4, 5  
and 6  
SSTL_18 interface  
tRAS lockout supported  
Operating temperature:  
Commercial (TA = 0°C to 70°C ; TC = 0°C to 85°C)  
Industrial (TA = -40°C to 85°C; TC = -40°C to 95°C)  
Automotive, A1 (TA = -40°C to 85°C; TC = -40°C to 95°C)  
Automotive, A2 (TA = -40°C to 105°C; TC = -40°C to  
105°C)  
Write Latency = Read Latency-1  
Programmable Burst Sequence: Sequential or  
Interleave  
OPTIONS  
Configuration:  
Programmable Burst Length: 4 and 8  
Automatic and Controlled Precharge Command  
Power Down Mode  
Auto Refresh and Self Refresh  
Refresh Interval: 7.8 s (8192 cycles/64 ms)  
ODT (On-Die Termination)  
Weak Strength Data-Output Driver Option  
Bidirectional differential Data Strobe (Single-  
ended data-strobe is an optional feature)  
On-Chip DLL aligns DQ and DQs transitions with  
CK transitions  
128Mx8 (16M x 8 x 8 banks)  
64Mx16 (8M x 16 x 8 banks)  
Package:  
60-ball TW-BGA for x8  
84-ball TW-BGA for x16  
Self-Refresh:  
Standard  
Low Power (L)  
ADDRESS TABLE  
Parameter  
Row Addressing  
Column Addressing  
Bank Addressing  
Precharge Addressing  
DQS# can be disabled for single-ended data  
strobe  
128Mx8  
A0-A13  
A0-A9  
BA0-BA2  
A10  
64Mx16  
A0-A12  
A0-A9  
BA0-BA2  
A10  
Read Data Strobe supported (x8 only)  
Differential clock inputs CK and CK#  
VDD and VDDQ = 1.8V ± 0.1V  
PASR (Partial Array Self Refresh)  
Clock Cycle Timing  
-3D  
-25E  
-25D  
Units  
Speed Grade  
CL-tRCD-tRP  
tCK (CL=3)  
DDR2-667D  
DDR2-800E  
DDR2-800D  
5-5-5  
5
6-6-6  
5
5-5-5  
5
tCK  
ns  
tCK (CL=4)  
tCK (CL=5)  
tCK (CL=6)  
tCK (CL=7)  
3.75  
3
3
3
333  
3.75  
3
2.5  
2.5  
400  
3.75  
2.5  
2.5  
2.5  
400  
ns  
ns  
ns  
ns  
Frequency (max)  
MHz  
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Rev. G  
3/25/2015  
1
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