Datasheet > IS43DR82560B-37CBLI

IS43DR82560B-37CBLI

更新时间： 2024-11-28 10:35:39

品牌	Logo	应用领域
美国芯成 - ISSI		动态存储器双倍数据速率
页数	文件大小	规格书
48页	1428K
描述
DDR DRAM, 256MX8, 0.5ns, CMOS, PBGA60, 10.50 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, TWBGA-60

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IS43/46DR82560B

IS43/46DR16128B

256Mx8, 128Mx16 DDR2 DRAM

ADVANCED INFORMATION

NOVEMBER 2012

DESCRIPTION

FEATURES

ISSI's 2Gb DDR2 SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

double-data rate architecture is essentially a 4n-prefetch

architecture, with an interface designed to transfer two

data words per clock cycle at the I/O balls.

•ꢀ Vdd = 1.8V 0.1V, Vddq = 1.8V 0.1V

•ꢀ JEDEC standard 1.8V I/O (SSTL_18-compatible)

•ꢀ Double data rate interface: two data transfers

per clock cycle

•ꢀ Differential data strobe (DQS, DQS)

•ꢀ 4-bit prefetch architecture

•ꢀ On chip DLL to align DQ and DQS transitions

ADDRESS TABLE

with CK

Parameter

256M x 8

128M x 16

•ꢀ 8 internal banks for concurrent operation

•ꢀ Programmable CAS latency (CL) 3, 4, 5, 6, and

Conﬁguration

32M x 8 x 8

banks

16M x 16 x 8

banks

Refresh Count

8K/64ms

7 supported

Row Addressing 32K (A0-A14) 16K (A0-A13)

•ꢀ Posted CAS and programmable additive latency

(AL) 0, 1, 2, 3, 4, 5, and 6 supported

•ꢀ WRITE latency = READ latency - 1 tCK

•ꢀ Programmable burst lengths: 4 or 8

Column

Addressing

1K (A0-A9)

Bank Addressing BA0-BA2

BA0-BA2

A10

Precharge

Addressing

A10

•ꢀ Adjustable data-output drive strength, full and

reduced strength options

•ꢀ On-die termination (ODT)

KEY TIMING PARAMETERS

OPTIONS

Speed Grade

-25D -25E -3D -37C

•ꢀ Conﬁguration(s):

tRCD

12.5

256Mx8 (32Mx8x8 banks) IS43/46DR82560B

128Mx16 (16Mx16x8 banks) IS43/46DR16128B

•ꢀ Package:

tRP

tRC

x8: 60-ball BGA (10.5mm x 13mm)

x16: 84-ball WBGA (10.5mm x 13.5mm)

Timing – Cycle time

2.5ns @CL=5 DDR2-800D

2.5ns @CL=6 DDR2-800E

3.0ns @CL=5 DDR2-667D

3.75ns @CL=4 DDR2-533C

tRAS

tCK @CL=3

tCK @CL=4

tCK @CL=5

tCK @CL=6

3.75 3.75 3.75 3.75

2.5

—

2.5

—

•ꢀ Temperature Range:

Commercial (0°C ≤ Tc ≤ 85°C)

Industrial (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)

Automotive, A1 (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)

Automotive, A2 (-40°C ≤ Tc; Ta ≤ 105°C)

Tc = Case Temp, Ta = Ambient Temp

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device speciﬁcation before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-

ably be expected to cause failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications

unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com

Rev. 00B

11/2/2012

12 3 4 5 6 7...48

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与IS43DR82560B-37CBLI相关器件

型号	品牌	获取价格	描述	数据表
IS43DR82560B-3DBL	ISSI	获取价格	IC DRAM 2G PARALLEL 60TWBGA
IS43DR82560B-3DBLI	ISSI	获取价格	IC DRAM 2G PARALLEL 60TWBGA
IS43DR82560B-3DBLI-TR	ISSI	获取价格	IC DRAM 2G PARALLEL 60TWBGA
IS43DR82560B-3DBL-TR	ISSI	获取价格	IC DRAM 2G PARALLEL 60TWBGA
IS43DR83200A	ISSI	获取价格	32Mx8, 16Mx16 DDR2 DRAM
IS43DR83200A-37CBI	ISSI	获取价格	32Mx8, 16Mx16 DDR2 DRAM
IS43DR83200A-37CBI-TR	ISSI	获取价格	DDR DRAM, 32MX8, 0.5ns, CMOS, PBGA60, 8 X 10.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, TWBGA-6
IS43DR83200A-37CBLI	ISSI	获取价格	32Mx8, 16Mx16 DDR2 DRAM
IS43DR83200A-3DBLI	ISSI	获取价格	32Mx8, 16Mx16 DDR2 DRAM
IS43DR83200A-3DBLI-TR	ISSI	获取价格	DDR DRAM, 32MX8, 0.45ns, CMOS, PBGA60, 8 X 10.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD F

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