IS43/46DR81280, IS43/46DR16640
PRELIMINARY INFORMATION
MARCH 2010
1Gb (x8, x16) DDR2 SDRAM
FEATURES
•
•
•
•
•
Clock frequency up to 533MHz
8 internal banks for concurrent operation
4‐bit prefetch architecture
Programmable CAS Latency: 3, 4, 5, 6 and 7
Programmable Additive Latency: 0, 1, 2, 3, 4, 5
and 6
•
•
•
Bidirectional differential Data Strobe (Single‐
ended data‐strobe is an optional feature)
On‐Chip DLL aligns DQ and DQs transitions with
CK transitions
DQS# can be disabled for single‐ended data
strobe
•
•
•
•
•
•
•
Read Data Strobe supported (x8 only)
Differential clock inputs CK and CK#
VDD and VDDQ = 1.8V ± 0.1V
PASR (Partial Array Self Refresh)
SSTL_18 interface
tRAS lockout supported
Operating temperature:
Commercial (TA = 0°C to +70°C ; TC = 0°C to 85°C)
Industrial (TA = ‐40°C to +85°C; TC = ‐40°C to 95°C)
Automotive, A1 (TA = ‐40°C to +85°C; TC = ‐40°C to
95°C)
•
•
Write Latency = Read Latency‐1
Programmable Burst Sequence: Sequential or
Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
•
•
•
•
•
•
•
•
Auto Refresh and Self Refresh
Refresh Interval: 7.8 μs (8192 cycles/64 ms)
OCD (Off‐Chip Driver Impedance Adjustment)
ODT (On‐Die Termination)
Weak Strength Data‐Output Driver Option
OPTIONS
ADDRESS TABLE
Parameter
128Mx8
A0‐A13
A0‐A9
BA0‐BA2
A10
64Mx16
A0‐A12
A0‐A9
BA0‐BA2
A10
• Configuration:
Row Addressing
Column Addressing
Bank Addressing
Precharge Addressing
−
−
128Mx8 (16M x 8 x 8 banks)
64Mx16 (8M x 16 x 8 banks)
• Package:
−
−
60‐ball FBGA for x8
84‐ball FBGA for x16
Clock Cycle Timing
‐37C
‐3D
‐25E
‐25D
‐19F
Units
Speed Grade
CL‐tRCD‐tRP
tCK (CL=3)
DDR2‐533C
DDR2‐667D
DDR2‐800E
DDR2‐800D
DDR2‐1066F
4‐4‐4
5
5‐5‐5
5
6‐6‐6
5
5‐5‐5
5
7‐7‐7
5
tCK
ns
tCK (CL=4)
3.75
3.75
3.75
3.75
3.75
ns
tCK (CL=5)
3.75
3.75
3.75
266
3
3
3
2.5
2.5
2.5
400
3
ns
ns
tCK (CL=6)
2.5
2.5
400
2.5
tCK (CL=7)
3
1.875
533
ns
Frequency (max)
333
MHz
Note: The ‐37C device specification is shown for reference only.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. – www.issi.com –
1
Rev. 00A, 3/17/2010