Datasheet > 存储 > DRAM> IS41C4100-35J

IS41C4100-35J

更新时间： 2024-02-15 07:25:50

品牌	Logo	应用领域
美国芯成 - ISSI		存储内存集成电路光电二极管动态存储器
页数	文件大小	规格书
19页	145K
描述
1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

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技术参数
数据手册

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IS41C4100-35J 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	TSOP, TSOP20/26,.36	Reach Compliance Code：	unknown
风险等级：	5.83	最长访问时间：	35 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	内存密度：	4194304 bit
内存集成电路类型：	EDO DRAM	内存宽度：	4
端子数量：	20	字数：	1048576 words
字数代码：	1000000	最高工作温度：	70 °C
最低工作温度：		组织：	1MX4
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP	封装等效代码：	TSOP20/26,.36
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
电源：	5 V	认证状态：	Not Qualified
刷新周期：	1024	自我刷新：	NO
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.11 mA	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

IS41C4100-35J 数据手册

IS41C4100

IS41LV4100

ISSI

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the t^REFrefresh requirement is exceeded.

2. V^IH(MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH

and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.

3. In addition to meeting the transition rate specification, all input signals must transit between V^IHand VIL (or between VIL and VIH) in

amonotonicmanner.

4. If CAS and RAS = V^IH, data output is High-Z.

5. If CAS = V^IL, data output may contain data from the last valid READ cycle.

6. Measured with a load equivalent to one TTL gate and 50 pF.

7. Assumes that t^RCD- tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by

the amount that t^RCDexceeds the value shown.

8. Assumes that t^RCD• tRCD (MAX).

9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the

data output buffer, CAS and RAS must be pulsed for t^CP.

10. Operation with the t^RCD(MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD

is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.

11. Operation within the t^RAD(MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD

is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.

12. Either t^RCHor tRRH must be satisfied for a READ cycle.

13. t^OFF(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.

14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS •

t^WCS(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD •

t^RWD(MIN), tAWD • tAWD (MIN) and tCWD • tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read

from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go

back to V^IH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled)

cycle.

15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.

16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a

LATE WRITE or READ-MODIFY-WRITE is not possible.

17. Write command is defined as WE going low.

18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t^ODand tOEH met (OE HIGH during WRITE cycle) in order to

ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS

remains LOW and OE is taken back to LOW after t^OEHis met.

19. The I/Os are in open during READ cycles once t^ODor tOFF occur.

20. The first χCAS edge to transition LOW.

21. The last χCAS edge to transition HIGH.

22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or

READ-MODIFY-WRITE cycles.

23. Last falling χCAS edge to first rising χCAS edge.

24. Last rising χCAS edge to next cycle’s last rising χCAS edge.

25. Last rising χCAS edge to first falling χCAS edge.

26. Each χCAS must meet minimum pulse width.

27. Last χCAS to go LOW.

28. I/Os controlled, regardless UCAS and LCAS.

29. The 3 ns minimum is a parameter guaranteed by design.

30. Enables on-chip refresh and address counters.

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00A

09/10/01

1...6 7 8910 11 12...19

中文翻译

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与IS41C4100-35J相关器件

型号	品牌	获取价格	描述	数据表
IS41C4100-35T	ICSI	获取价格	1Mx4 bit Dynamic RAM with EDO Page Mode
IS41C4100-60J	ISSI	获取价格	1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C4100-60JI	ISSI	获取价格	1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C44002	ICSI	获取价格	4Mx4 bit Dynamic RAM with EDO Page Mode
IS41C44002	ISSI	获取价格	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C44002-50J	ISSI	获取价格	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C44002-50JI	ISSI	获取价格	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C44002-50T	ETC	获取价格	x4 EDO Page Mode DRAM
IS41C44002-50TI	ISSI	获取价格	EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, TSOP2-24
IS41C44002-60J	ISSI	获取价格	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

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