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IPUG110

更新时间： 2023-12-20 18:46:13

品牌	Logo	应用领域
莱迪思 - LATTICE		动态存储器双倍数据速率光电二极管
页数	文件大小	规格书
39页	3055K
描述
LPDDR3 SDRAM Controller IP Core User's Guide

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Chapter 1:

Introduction

The Lattice Low Power Double Data Rate (LPDDR3) Synchronous Dynamic Random Access Memory (SDRAM)

Controller is a general-purpose memory controller that interfaces with industry standard LPDDR3 memory devices

compliant with JESD209-3, LPDDR3 SDRAM Standard, and provides a generic command interface to user appli-

cations. LPDDR3 SDRAM is the next-generation Low Power SDRAM memory technology which offers a higher

data rate, higher density, greater bandwidth and power efficiency. This core reduces the effort required to integrate

the LPDDR3 memory controller with the user application design and minimizes the need to directly deal with the

LPDDR3 memory interface.

Quick Facts

Table 1-1 gives quick facts about the LPDDR3 SDRAM Controller IP core.

Table 1-1. LPDDR3 IP Core Quick Facts¹

LPDDR3 IP Configuration

x16

x32

Core

Requirements

FPGA Families

Supported

ECP5™

Minimal Device 

Needed

LFE5U-25F-6MG285C/

LAE5UM-25F-6MG285E

LFE5U-25F-6MG285C/

LAE5UM-25F-6MG285E¹

Resource 

Utilization

Targeted Device

Data Path Width

LUTs

LFE5UM-85F-8BG756CES

2241

2462

sysMEM EBRs

Registers

1599

1937

Design Tool 

Support

Lattice

Implementation

Lattice Diamond^®3.3

Synopsys^®Synplify Pro^®for Lattice I-2014.03L-SP1

Lattice Synthesis Engine (LSE)

Aldec^®Active-HDL^®9.3 Lattice Edition II Mixed Language

Mentor Graphics^®ModelSim^®SE PLUS 6.5 or later

Synthesis

Simulation

1. LFE5U-25F-6MG381C/LAE5UM-25F-6MG381E for the core evaluation project inside a generated core

Features

The LPDDR3 SDRAM Controller IP core supports the following features:

• Support for all ECP5 devices

• Interfaces to industry standard LPDDR3 SDRAM components and modules compliant with JESD209-3,

LPDDR3 SDRAM Standard

• Interfaces to LPDDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices

• Supports memory data path widths of 16 and 32 bits

• Supports x16 and x32 device configurations

• Supports single rank of an LPDDR3 device (one chip select)

• Supports burst lengths of eight (fixed)

IPUG110_1.0, September 2014

LPDDR3 SDRAM Controller IP Core User’s Guide

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