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IN74AC74N PDF预览

IN74AC74N

更新时间: 2024-11-05 22:48:07
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INTEGRAL 触发器
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5页 168K
描述
Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

IN74AC74N 数据手册

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TECHNICAL DATA  
IN74AC74  
Dual D Flip-Flop with Set and Reset  
High-Speed Silicon-Gate CMOS  
The IN74AC74 is identical in pinout to the LS/ALS74,  
HC/HCT74. The device inputs are compatible with standard CMOS  
outputs; with pullup resistors, they are compatible with LS/ALS  
outputs.  
This device consists of two D flip-flops with individual Set, Reset,  
and Clock inputs. Information at a D-input is transferred to the  
corresponding Q output on the next positive going edge of the clock  
input. Both Q and Q outputs are available from each flip-flop. The Set  
and Reset inputs are asynchronous.  
ORDERING INFORMATION  
IN74AC74N Plastic  
IN74AC74D SOIC  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA; 0.1 µA @ 25°C  
High Noise Immunity Characteristic of CMOS Devices  
TA = -40° to 85° C for all  
packages  
Outputs Source/Sink 24 mA  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
Clock  
Outputs  
Set  
L
Reset  
H
Data  
X
Q
Q
X
X
X
H
L
H*  
H
L
L
H
H*  
L
H
L
L
X
L
X
H
H
H
H
H
H
H
H
L
H
H
L
X
No Change  
No Change  
No Change  
H
H
X
PIN 14 =VCC  
PIN 7 = GND  
H
X
*Both outputs will remain high as long as Set  
and Reset are low, but the output states are  
unpredictable if Set and Reset go high  
simultaneously.  
X = don’t care  
99  

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