Datasheet > IN74ACT109N

IN74ACT109N

更新时间： 2024-11-06 05:39:19

品牌	Logo	应用领域
IKSEMICON		触发器栅
页数	文件大小	规格书
6页	190K
描述
Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

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IN74ACT109N 数据手册

TECHNICAL DATA

IN74ACT109

Dual J-K Flip-Flop

with Set and Reset

High-Speed Silicon-Gate CMOS

The IN74ACT109 is identical in pinout to the LS/ALS109,

HC/HCT109. The IN74ACT109 may be used as a level converter for

interfacing TTL or NMOS outputs to High Speed CMOS inputs.

This device consists of two J-K flip-flops with individual set, reset,

and clock inputs. Changes at the inputs are reflected at the outputs with

the next low-to-high transition of the clock. Both Q to Q outputs are

available from each flip-flop.

ORDERING INFORMATION

IN74ACT109N Plastic

IN74ACT109D SOIC

•

TTL/NMOS Compatible Input Levels

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 4.5 to 5.5 V

Low Input Current: 1.0 µA; 0.1 µA @ 25°C

Outputs Source/Sink 24 mA

T_A= -40° to 85° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

Outputs

Set Reset

H^*

Toggle

No Change

PIN 16=V_CC

PIN 8 = GND

No Change

X = Don’t care

^*Both outputs will remain high as long as Set and

Reset are low, but the output states are

unpredictable if Set and Reset go high

simultaneously.

Rev. 00

12 3 4 5 6

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与IN74ACT109N相关器件

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IN74ACT10D	INTEGRAL	获取价格	Triple 3-Input NAND Gate
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IN74ACT11	INTEGRAL	获取价格	TRIPLE 3-INPUT AND GATE
IN74ACT112	IKSEMICON	获取价格	Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
IN74ACT112	INTEGRAL	获取价格	DUAL J-K FLIP-FLOP WITH SET AND RESET
IN74ACT112D	IKSEMICON	获取价格	Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
IN74ACT112D	INTEGRAL	获取价格	DUAL J-K FLIP-FLOP WITH SET AND RESET
IN74ACT112N	INTEGRAL	获取价格	DUAL J-K FLIP-FLOP WITH SET AND RESET
IN74ACT112N	IKSEMICON	获取价格	Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
IN74ACT11D	INTEGRAL	获取价格	TRIPLE 3-INPUT AND GATE