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IM4J-65608V-35 PDF预览

IM4J-65608V-35

更新时间: 2024-11-04 20:25:11
品牌 Logo 应用领域
TEMIC 静态存储器内存集成电路
页数 文件大小 规格书
10页 193K
描述
Standard SRAM, 128KX8, 35ns, CMOS, CDSO32,

IM4J-65608V-35 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
最长访问时间:35 nsI/O 类型:COMMON
JESD-30 代码:R-CDSO-N32JESD-609代码:e0
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端口数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
输出特性:3-STATE可输出:YES
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC32,.42SQ,40封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified最大待机电流:0.00004 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.14 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:1 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

IM4J-65608V-35 数据手册

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M65608  
128 K x 8 Ultimate CMOS SRAM  
Introduction  
The M 65608 is a very low power CMOS static RAM  
organized as 131072 × 8 bits. It is manufactured using  
the TEMIC high performance CMOS technology named  
SCMOS.  
current (Typical value = 0.2 µA) with a fast access time  
at 25 ns over the full commercial temperature range.  
The high stability of the 6T cell provides excellent  
protection against soft errors due to noise.  
With this process, TEMIC brings the solution to  
applications where fast computing is as mandatory as  
low consumption, such as aerospace electronics,  
portable instruments, or embarked systems.  
For military/space applications that demand superior  
levels of performance and reliability the M 65608 is  
processed according to the methods of the latest revision  
of the MIL STD 883 (class B or S) and/or ESA SCC  
9000.  
Utilizing an array of six transistors (6T) memory cells,  
the M 65608 combines an extremely low standby supply  
Features  
D Access time : commercial : 25/30/35/45 ns  
industrial and military : 25/30/35/45 ns  
D Very low power consumption  
active : 250 mW (Typ)  
D TTL compatible inputs and outputs  
D Asynchronous  
D Single 5 volt supply  
D Equal cycle and access time  
D Gated inputs :  
standby : 1 µW (Typ)  
data retention : 0.5 µW (Typ)  
no pull-up/down  
D Wide temperature Range : –55 To +125°C  
resistors are required  
D 400 Mils width package  
Interface  
Block Diagram  
MATRA MHS  
1
Rev. B (23/03/96)  

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