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IDT74ALVCH16501PV8 PDF预览

IDT74ALVCH16501PV8

更新时间： 2024-09-16 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 113K
描述
Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56

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IDT74ALVCH16501PV8 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP,
针数：56Reach Compliance Code：compliant
风险等级：5.92其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e0长度：18.415 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER湿度敏感等级：1
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：225传播延迟（tpd）：5.6 ns
认证状态：Not Qualified座面最大高度：2.794 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20宽度：7.5 mm
Base Number Matches：1

IDT74ALVCH16501PV8 数据手册

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3.3V CMOS 18-BIT  
IDT74ALVCH16501  
UNIVERSAL BUS TRANS-  
CEIVER WITH 3-STATE  
OUTPUTS AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
This 18-bit universal bus transceiver is built using advanced dual  
–
–
–
0.5 MICRON CMOS Technology  
TypicaltSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
metal CMOS technology. Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and  
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device  
operates in the transparent mode when LEAB is high. When LEAB is low,  
the A data is latched if CLKAB is held at a high or low logic level. If LEAB  
is low, the A data is stored in the latch/flip-flop on the low-to-high transition  
of CLKAB. When OEAB is high, the outputs are active. When OEAB is  
low, the outputs are in the high-impedance state.  
–
–
–
–
–
–
–
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
Data flow for B to A is similiar to that of A to B but uses OEBA, LEBA,  
and CLKBA. The output enables are complementary (OEAB is active  
high and OEBA is active low).  
Drive Features for ALVCH16501:  
–
–
High Output Drivers: ±24mA  
Suitable for heavy loads  
The ALVCH16501 has been designed with a ±24mA output driver.  
This driver is capable of driving a moderate to heavy load while  
maintaining speed performance.  
APPLICATIONS:  
• 3.3V High Speed Systems  
• 3.3V and lower voltage computing systems  
The ALVCH16501 has “bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
Functional Block Diagram  
1
OEAB  
55  
CLKAB  
2
LEAB  
28  
LEBA  
30  
CLKBA  
27  
OEBA  
3
A1  
1D  
54  
B1  
C1  
CLK  
1D  
C1  
CLK  
TO 17 OTHER CHANNELS  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
APRIL 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4738/-  
1234567

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