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IDT74ALVCH162260PF8 PDF预览

IDT74ALVCH162260PF8

更新时间: 2024-11-21 20:07:11
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路电视
页数 文件大小 规格书
8页 77K
描述
Multiplexer And Demux/Decoder, ALVC/VCX/A Series, 12-Func, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56

IDT74ALVCH162260PF8 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G56JESD-609代码:e0
长度:11.3 mm逻辑集成电路类型:MULTIPLEXER AND DEMUX/DECODER
功能数量:12端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.4 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

IDT74ALVCH162260PF8 数据手册

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3.3V CMOS 12-BIT TO 24-BIT  
IDT74ALVCH162260  
MULTIPLEXED D-TYPE LATCH  
WITH 3-STATE OUTPUTS AND  
BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
ThismultiplexedD-typelatchisbuiltusingadvanceddualmetalCMOS  
technology. The ALVCH162260 is used in applications in which two  
separate data paths mustbe multiplexedonto,ordemultiplexedfrom,a  
singledatapath.Typicalapplicationsincludemultiplexingand/ordemultiplexing  
addressanddatainformationinmicroprocessororbus-interfaceapplica-  
tions.This device alsois usefulinmemory-interleavingapplications.  
Three 12-bit I/O ports (A1A12, 1B1–1B12, and 2B1–2B12) are  
available for address and/or data transfer. The output-enable (OE1B,  
OE2B,andOEA)inputs controlthebus transceiverfunctions.The OE1B  
andOE2B controlsignals alsoallowbankcontrolinthe A-to-Bdirection.  
Address and/ordatainformationcanbestoredusingtheinternalstorage  
latches.The latch-enable (LE1B,LE2B,LEA1B,andLEA2B)inputs are  
usedtocontroldatastorage.Whenthelatch-enableinputishigh,thelatch  
is transparent.Whenthelatch-enableinputgoes low,thedatapresentat  
the inputs is latched and remains latched until the latch-enable input is  
returnedhigh.  
Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
Available in SSOP, TSSOP, and TVSOP packages  
DRIVE FEATURES:  
• Balanced Output Drivers: ±12mA (A port)  
High Output Drivers: ±24mA (B port)  
APPLICATIONS:  
The ALVCH162260has series resistors inthe device outputstructure  
oftheB”portwhichwillsignificantlyreducelinenoisewhenusedwithlight  
loads. This driverhas beendesignedtodrive ±12mAatthe designated  
threshold levels. The A” port has a ± 24mA driver.  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
The ALVCH162260has bus-hold”whichretains the inputs’laststate  
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputs  
andeliminates the needforpull-up/downresistors.  
FUNCTIONALBLOCKDIAGRAM  
29  
OE1B  
30  
A-1B  
LEA1B  
1B1:12  
12  
LATCH  
2
1B-A  
LE1B  
12  
LATCH  
12  
12  
28  
SEL  
1
OEA  
1
0
M
U
X
A1:12  
12  
12  
12  
2B-A  
LATCH  
27  
12  
LE2B  
A-2B  
LATCH  
2B1:12  
55  
56  
12  
LEA2B  
OE2B  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MARCH 1999  
1
© 1999 Integrated Device Technology, Inc.  
DSC-4628/2  

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