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IDT74ALVCH162268PAG PDF预览

IDT74ALVCH162268PAG

更新时间： 2024-11-18 20:09:31
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路
页数 文件大小 规格书
8页 84K
描述
Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, TSSOP-56

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IDT74ALVCH162268PAG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.73其他特性：WITH SYNCHRONOUS O/P ENABLES AND MUX SELECT
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e3长度：14 mm
逻辑集成电路类型：BUS EXCHANGER湿度敏感等级：1
位数：12功能数量：1
端口数量：3端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：5.4 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：6.1 mm
Base Number Matches：1

IDT74ALVCH162268PAG 数据手册

 浏览型号IDT74ALVCH162268PAG的Datasheet PDF文件第2页浏览型号IDT74ALVCH162268PAG的Datasheet PDF文件第3页浏览型号IDT74ALVCH162268PAG的Datasheet PDF文件第4页浏览型号IDT74ALVCH162268PAG的Datasheet PDF文件第5页浏览型号IDT74ALVCH162268PAG的Datasheet PDF文件第6页浏览型号IDT74ALVCH162268PAG的Datasheet PDF文件第7页 
3.3V CMOS 12-BIT TO 24-BIT  
IDT74ALVCH162268  
REGISTERED BUS EX-  
CHANGER WITH 3-STATE  
OUTPUTS AND BUS-HOLD  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
This 12-bit to 24-bit registered bus exchanger is built using advanced  
dualmetalCMOStechnology. Thisdeviceisusedforapplicationsin which  
data must be transferred from a narrow high-speed bus to a wide, lower-  
frequency bus.  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• VCC = 2.5V ± 0.2V  
• CMOS power levels (0.4µ W typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in TSSOP and TVSOP packages  
The ALVCH162268 device provides synchronous data exchange be-  
tween the two ports. Data is stored in the internal registers on the low-to-  
high transition of the clock (CLK) input when the appropriate clock-enable  
(CLKEN)inputsarelow.Theselect(SEL)lineissynchronouswithCLKand  
selects 1B or 2B input data for the A outputs. For data transfer in the A-to-  
Bdirection,atwo-stagepipelineisprovidedintheA-to-1Bpath,withasingle  
storage register in the A-to-2B path. Proper control of these inputs allows  
twosequential12-bitwordstobepresentedasa24-bitwordontheB-port.  
Data flow is controlled by the active-low output enables (OEA and OEB).  
These control terminals are registered to synchronize the bus-direction  
changes with CLK.  
DRIVE FEATURES:  
• High Output Drivers: ±24mA (A port)  
• Balanced Output Drivers: ±12mA (B port)  
TheALVCH162268hasseriesresistorsinthedeviceoutputstructureof  
the “B” port which will significantly reduce line noise when used with light  
loads. This driver has been designed to drive ±12mA at the designated  
threshold levels. The “A” port has a ±24mA driver.  
APPLICATIONS:  
• 3.3V high speed systems  
• 3.3V and lower voltage computing systems  
The ALVCH162268 has “bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
FUNCTIONALBLOCKDIAGRAM  
29  
CLK  
2
CLKEN1B  
27  
CLKEN2B  
30  
CLKENA1  
55  
CLKENA2  
C1  
1D  
56  
OEB  
C1  
1D  
28  
SEL  
1
OEA  
CE  
C1  
1D  
1D  
C1  
23  
1B1  
CE  
0
1
C1  
8
A1  
6
2B1  
1D  
CE  
CE  
C1  
1D  
C1  
1D  
CE  
C1  
1D  
1 of 12 Channels  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2004  
1
© 2004 Integrated Device Technology, Inc.  
DSC-4535/2  
12345678

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IDT74ALVCH162344PA IDT

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IDT74ALVCH162344PF8 IDT

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