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IDT74ALVCH162268PA PDF预览

IDT74ALVCH162268PA

更新时间: 2024-10-01 21:15:19
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路
页数 文件大小 规格书
8页 147K
描述
Bus Exchanger, ALVC/VCX/A Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, TSSOP-56

IDT74ALVCH162268PA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP56,.3,20
针数:56Reach Compliance Code:not_compliant
风险等级:5.76其他特性:WITH SYNCHRONOUS O/P ENABLES AND MUX SELECT
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:14 mm
逻辑集成电路类型:BUS EXCHANGER湿度敏感等级:1
位数:12功能数量:1
端口数量:3端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:3.3 V传播延迟(tpd):5.4 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Other Logic ICs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:6.1 mmBase Number Matches:1

IDT74ALVCH162268PA 数据手册

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3.3V CMOS 12-BIT TO 24-BIT  
REGISTERED BUS EX-  
IDT74ALVCH162268  
CHANGER WITH 3-STATE  
OUTPUTS AND BUS-HOLD  
which data must be transferred from a narrow high-speed bus to a wide,  
lower-frequency bus.  
FEATURES:  
0.5 MICRON CMOS Technology  
Typical tSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
The ALVCH162268 device provides synchronous data exchange  
between the two ports. Data is stored in the internal registers on the low-  
to-high transition of the clock (CLK) input when the appropriate clock-  
enable (CLKEN) inputs are low. The select (SEL) line is synchronous  
with CLK and selects 1B or 2B input data for the A outputs. For data  
transfer in the A-to-B direction, a two-stage pipeline is provided in the A-  
to-1B path, with a single storage register in the A-to-2B path. Proper  
control of these inputs allows two sequential 12-bit words to be presented  
as a 24-bit word on the B-port. Data flow is controlled by the active-low  
output enables (OEA and OEB). These control terminals are registered  
to synchronize the bus-direction changes with CLK.  
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
Drive Features for ALVCH162268:  
High Output Drivers: ± 24mA (A port)  
Balanced Output Drivers: ± 12mA (B port)  
The ALVCH162268 has series resistors in the device output structure  
ofthe Bportwhichwillsignificantlyreduce line noise whenusedwithlight  
loads. This driver has been designed to drive ±12mA at the designated  
threshold levels. The A” port has a ±24mA driver.  
APPLICATIONS:  
3.3V High Speed Systems  
The ALVCH162268 has bus-hold” which retains the inputs’ last state  
whenever the input bus goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
3.3V and lower voltage computing systems  
DESCRIPTION:  
This 12-bit to 24-bit registered bus exchanger is built using advanced  
dual metal CMOS technology. This device is used for applications in  
FUNCTIONALBLOCKDIAGRAM  
29  
CLK  
2
CLKEN1B  
27  
CLKEN2B  
30  
CLKENA1  
55  
CLKENA2  
C1  
1D  
56  
OEB  
C1  
1D  
28  
SEL  
1
OEA  
CE  
C1  
1D  
1D  
C1  
23  
1B1  
CE  
0
1
C1  
8
A1  
6
2B1  
1D  
CE  
CE  
C1  
1D  
C1  
1D  
CE  
C1  
1D  
1 of 12 Channels  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
OCTOBER 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4535/-  

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