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IDT72V70200TFG PDF预览

IDT72V70200TFG

更新时间: 2024-11-15 21:17:31
品牌 Logo 应用领域
艾迪悌 - IDT 电信电信集成电路
页数 文件大小 规格书
23页 131K
描述
Digital Time Switch, PQFP100, PLASTIC, TQFP-100

IDT72V70200TFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:PLASTIC, TQFP-100针数:100
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.17JESD-30 代码:R-PQFP-G100
JESD-609代码:e3长度:20 mm
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT72V70200TFG 数据手册

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PRELIMINARY  
IDT72V70200  
3.3 VOLT Time Slot Interchange  
Digital Switch  
512 x 512  
100-pin Ball Grid Array (PBGA), 100-pin Thin Plastic Quad  
Flatpack (TQFP) and 100-pin Thin Quad Flatpack (TQFP)  
3.3V Power Supply  
FEATURES:  
512 x 512 channel non-blocking switching at 2.048 Mb/s  
Per-channel variable or constant throughput delay  
Automatic identification of ST-BUS®/GCI interfaces  
Accept 16 serial data streams of 2.048 Mb/s  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel high impedance output control  
Per-channel Processor Mode  
DESCRIPTION:  
The IDT72V70200 is a non-blocking digital switch that has a capacity of  
512x512channels at2.048Mb/s.Someofthemainfeatures are:program-  
mablestreamandchannelcontrol,ProcessorMode,inputoffsetdelayandhigh-  
impedanceoutputcontrol.  
Control interface compatible to Intel/Motorola CPUs  
Connection memory block programming  
IEEE-1149.1 (JTAG) Test Port  
Per-streaminputdelaycontrolis providedformanaginglarge multi-chip  
switchesthattransportbothvoicechannelandconcatenateddatachannels.In  
addition,inputstreamscanbeindividuallycalibratedforinputframeoffset.  
Available in 84-pin Plastic Leaded Chip Carrier (PLCC),  
FUNCTIONALBLOCKDIAGRAM  
RESET  
TRST  
VCC GND  
TMS  
TDI  
TDO TCK  
IC  
ODE  
Test Port  
Loopback  
RX0  
TX0  
TX1  
RX1  
RX2  
RX3  
TX2  
TX3  
RX4  
TX4  
Receive  
Serial Data  
Streams  
RX5  
RX6  
Transmit  
Serial Data  
Streams  
TX5  
TX6  
Output  
MUX  
RX7  
Data Memory  
TX7  
RX8  
TX8  
RX9  
TX9  
RX10  
RX11  
RX12  
RX13  
RX14  
RX15  
TX10  
TX11  
TX12  
TX13  
TX14  
TX15  
Connection  
Memory  
Internal  
Registers  
Timing Unit  
Microprocessor Interface  
DS/  
RD  
F0i  
DTA  
D8-D15/  
CLK  
FE  
IC  
AS/ IM  
ALE  
R/W/ A0-A7  
WR  
CCO  
CS  
AD0-AD7  
5711 drw01  
MARCH 2000  
1
2000 Integrated Device Technology, Inc.  
DSC-5711/2  

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