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IDT72V70800TF8 PDF预览

IDT72V70800TF8

更新时间: 2024-09-28 21:20:39
品牌 Logo 应用领域
艾迪悌 - IDT 电信电信集成电路
页数 文件大小 规格书
21页 138K
描述
Digital Time Switch, PQFP64, STQFP-64

IDT72V70800TF8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:STQFP-64针数:64
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.06JESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:10 mm
湿度敏感等级:3功能数量:1
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP64,.47SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Other Telecom ICs最大压摆率:0.045 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:DIGITAL TIME SWITCH温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:10 mm
Base Number Matches:1

IDT72V70800TF8 数据手册

 浏览型号IDT72V70800TF8的Datasheet PDF文件第2页浏览型号IDT72V70800TF8的Datasheet PDF文件第3页浏览型号IDT72V70800TF8的Datasheet PDF文件第4页浏览型号IDT72V70800TF8的Datasheet PDF文件第5页浏览型号IDT72V70800TF8的Datasheet PDF文件第6页浏览型号IDT72V70800TF8的Datasheet PDF文件第7页 
3.3 VOLT TIME SLOT INTERCHANGE  
DIGITAL SWITCH  
IDT72V70800  
512 x 512  
64-pin Small Thin Quad Flatpack (STQFP)  
3.3V Power Supply  
Operating Temperature Range -40°C to +85°C  
3.3V I/O with 5V Tolerant Inputs  
FEATURES:  
512 x 512 channel non-blocking switching at 8.192 Mb/s  
Per-channel variable or constant throughput delay  
Automatic identification of ST-BUS®/GCI interfaces  
Accepts 4 Serial Data Streams of 8.192 Mb/s  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel high impedance output control  
Per-channel Processor Mode  
DESCRIPTION:  
The IDT72V70800 is a non-blocking digital switch that has a capacity of  
512x512channelsataserialbitrateof8.192Mb/s.Someofthemainfeatures  
are:programmablestreamandchannelcontrol,ProcessorMode,inputoffset  
delayandhigh-impedanceoutputcontrol.  
Control interface compatible to Intel/Motorola CPUs  
Connection memory block programming  
Per-stream input delay control is provided for managing large multi-chip  
switchesthattransportbothvoicechannelandconcatenateddatachannels.In  
addition,inputstreamscanbeindividuallycalibratedforinputframeoffset.  
· Available in 64-pin Thin Plastic Quad Flatpack (TQFP) and  
FUNCTIONALBLOCKDIAGRAM  
RESET  
VCC GND  
ODE  
Loopback  
RX0  
RX1  
RX2  
RX3  
TX0  
TX1  
TX2  
TX3  
Output  
MUX  
Data Memory  
Transmit  
Serial Data  
Streams  
Receive  
Serial Data  
Streams  
Connection  
Memory  
Internal  
Registers  
Timing Unit  
Microprocessor Interface  
DS/  
RD  
F0i  
DTA  
D8-D15/  
CLK  
FE/  
HCLK  
WFPS  
AS/ IM  
ALE  
R/W/ A0-A7  
WR  
CS  
AD0-AD7  
5709 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS® isatrademarkofMitelCorp.  
MARCH 2003  
1
© 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5709/4  

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