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IDT72V70810PFG8 PDF预览

IDT72V70810PFG8

更新时间: 2024-11-15 21:05:59
品牌 Logo 应用领域
艾迪悌 - IDT 电信电信集成电路
页数 文件大小 规格书
22页 151K
描述
Digital Time Switch, PQFP64, PLASTIC, TQFP-64

IDT72V70810PFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, TQFP-64针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.77
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:14 mm湿度敏感等级:3
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT72V70810PFG8 数据手册

 浏览型号IDT72V70810PFG8的Datasheet PDF文件第2页浏览型号IDT72V70810PFG8的Datasheet PDF文件第3页浏览型号IDT72V70810PFG8的Datasheet PDF文件第4页浏览型号IDT72V70810PFG8的Datasheet PDF文件第5页浏览型号IDT72V70810PFG8的Datasheet PDF文件第6页浏览型号IDT72V70810PFG8的Datasheet PDF文件第7页 
3.3 VOLT TIME SLOT INTERCHANGE  
DIGITAL SWITCH  
1,024 x 1,024  
IDT72V70810  
64-pin Small Thin Quad Flatpack (STQFP)  
3.3V Power Supply  
Operating Temperature Range -40°C to +85°C  
3.3V I/O with 5V Tolerant Inputs  
FEATURES:  
1,024 x 1,024 channel non-blocking switching at 8.192 Mb/s  
Per-channel variable or constant throughput delay  
Automatic identification of ST-BUS®/GCI interfaces  
Accepts 8 Serial Data Streams of 8.192 Mb/s  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel high impedance output control  
Per-channel Processor Mode  
DESCRIPTION:  
The IDT72V70810 is a non-blocking digital switch that has a capacity of  
1,024 x 1,024 channels at a serial bit rate of 8.192 Mb/s. Some of the main  
features are: programmable stream and channel control, Processor Mode,  
inputoffsetdelayandhigh-impedanceoutputcontrol.  
Per-streaminputdelaycontrolis providedformanaginglarge multi-chip  
switchesthattransportbothvoicechannelandconcatenateddatachannels.In  
addition,inputstreamscanbeindividuallycalibratedforinputframeoffset.  
Control interface compatible to Intel/Motorola CPUs  
Connection memory block programming  
Available in 64-pin Thin Plastic Quad Flatpack (TQFP) and  
FUNCTIONALBLOCKDIAGRAM  
RESET  
VCC GND  
ODE  
Loopback  
RX0  
RX1  
RX2  
RX3  
RX4  
RX5  
RX6  
RX7  
TX0  
TX1  
TX2  
TX3  
TX4  
TX5  
TX6  
TX7  
Output  
MUX  
Data Memory  
Transmit  
Serial Data  
Streams  
Receive  
Serial Data  
Streams  
Connection  
Memory  
Internal  
Registers  
Timing Unit  
Microprocessor Interface  
DS/  
RD  
F0i  
DTA  
CLK  
FE/  
HCLK  
WFPS  
AS/ IM  
ALE  
R/W/ A0-A7  
WR  
CCO  
CS  
D8-D15/  
AD0-AD7  
5710 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUSisatrademarkofMitelCorp.  
MARCH 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5710/4  

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