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IDT72V2101L20PFG8 PDF预览

IDT72V2101L20PFG8

更新时间: 2024-11-21 14:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
27页 256K
描述
FIFO, 256KX9, 12ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64

IDT72V2101L20PFG8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.43
Is Samacsys:N最长访问时间:12 ns
其他特性:RETRANSMIT; AUTO POWER DOWN周期时间:20 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
长度:14 mm内存密度:2359296 bit
内存宽度:9湿度敏感等级:3
功能数量:1端子数量:64
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX9
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT72V2101L20PFG8 数据手册

 浏览型号IDT72V2101L20PFG8的Datasheet PDF文件第2页浏览型号IDT72V2101L20PFG8的Datasheet PDF文件第3页浏览型号IDT72V2101L20PFG8的Datasheet PDF文件第4页浏览型号IDT72V2101L20PFG8的Datasheet PDF文件第5页浏览型号IDT72V2101L20PFG8的Datasheet PDF文件第6页浏览型号IDT72V2101L20PFG8的Datasheet PDF文件第7页 
3.3 VOLT HIGH DENSITY CMOS  
SUPERSYNC FIFO™  
262,144 x 9  
IDT72V2101  
IDT72V2111  
524,288 x 9  
simultaneously)  
Available in the 64-pin Thin Quad Flat Pack (TQFP)  
High-performance submicron CMOS technology  
FEATURES:  
Choose among the following memory organizations:  
IDT72V2101  
IDT72V2111  
262,144 x 9  
524,288 x 9  
DESCRIPTION:  
Pin-compatible with the IDT72V261/72V271 and the IDT72V281/  
72V291 SuperSync FIFOs  
The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS  
First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These  
FIFOs offer numerous improvements over previous SuperSync FIFOs,  
includingthefollowing:  
10ns read/write cycle time (6.5ns access time)  
Fixed, low first word data latency time  
5V input tolerant  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable settings  
Retransmit operation with fixed, low first word data latency time  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of two preselected offsets  
Program partial flags by either serial or parallel means  
SelectIDTStandardtiming(usingEFandFFflags)orFirstWordFall  
Through timing (using OR and IR flags)  
Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas  
been removed. The Frequency Select pin (FS) has been removed, thus  
itis nolongernecessarytoselectwhichofthe twoclockinputs, RCLKor  
WCLK, is runningatthe higherfrequency.  
The period required by the retransmit operation is now fixed and short.  
Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan  
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable  
clockcyclecountingdelayassociatedwiththelatencyperiodfound on  
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)  
SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecommu-  
nications,datacommunicationsandotherapplicationsthatneedtobufferlarge  
amountsofdata.  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
Independent Read and Write clocks (permit reading and writing  
FUNCTIONAL BLOCK DIAGRAM  
D0 -D8  
WEN  
WCLK  
LD  
SEN  
OFFSET REGISTER  
INPUT REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
HF  
RAM ARRAY  
262,144 x 9  
524,288 x 9  
FWFT/SI  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
RT  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
Q0 -Q8  
4669 drw 01  
OE  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.  
DECEMBER 2008  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
DSC-4669/4  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  

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