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IDT72V2103L6PFI PDF预览

IDT72V2103L6PFI

更新时间: 2024-11-23 22:34:11
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
46页 446K
描述
3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO

IDT72V2103L6PFI 数据手册

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3.3 VOLT HIGH-DENSITY SUPERSYNC II™  
NARROW BUS FIFO  
131,072 x 18/262,144 x 9  
262,144 x 18/524,288 x 9  
IDT72V2103  
IDT72V2113  
FEATURES:  
Partial Reset clears data, but retains programmable settings  
Choose among the following memory organizations:  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
IDT72V2103  
IDT72V2113  
131,072 x 18/262,144 x 9  
262,144 x 18/524,288 x 9  
Functionally compatible with the IDT72V255LA/72V265LA and Selectable synchronous/asynchronous timing modes for Almost-  
IDT72V275/72V285 SuperSync FIFOs  
Empty and Almost-Full flags  
Up to 166 MHz Operation of the Clocks  
Program programmable flags by either serial or parallel means  
User selectable Asynchronous read and/or write ports (BGA Only) Select IDT Standard timing (using EF and FF flags) or First Word  
7.5 ns read/write cycle time (5.0 ns access time)  
User selectable input and output port bus-sizing  
- x9 in to x9 out  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
- x9 in to x18 out  
- x18 in to x9 out  
- x18 in to x18 out  
JTAG port, provided for Boundary Scan function (BGA Only)  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
Big-Endian/Little-Endian user selectable byte representation  
5V tolerant inputs  
Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball  
Grid Array (BGA) (with additional features)  
Fixed, low first word latency  
Zero latency retransmit  
Pin compatible to the SuperSync II (IDT72V223/72V233/72V243/  
72V253/72V263/72V273/72V283/72V293)family  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
FUNCTIONAL BLOCK DIAGRAM  
D0 -Dn (x9 or x18)  
LD SEN  
*Available on the  
BGA package only.  
WEN WCLK/WR  
*
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
ASYW  
HF  
*
RAM ARRAY  
FWFT/SI  
PFM  
131,072 x 18 or 262,144 x 9  
262,144 x 18 or 524,288 x 9  
FSEL0  
FSEL1  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
RT  
RM  
ASYR  
READ  
CONTROL  
LOGIC  
OUTPUT REGISTER  
IW  
OW  
BUS  
*
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK/RD  
*
REN  
TCK  
*
*
TRST  
JTAG CONTROL  
(BOUNDARY  
SCAN)  
*
TMS  
6119 drw01  
*
TDI  
*
Q0 -Qn (x9 or x18)  
OE  
TDO  
*
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.  
SEPTEMBER 2003  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6119/10  

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