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IDT72V2105L10PFG8 PDF预览

IDT72V2105L10PFG8

更新时间: 2024-11-21 15:34:47
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
26页 232K
描述
FIFO, 256KX18, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64

IDT72V2105L10PFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP,针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.47
最长访问时间:6.5 ns其他特性:EASILY EXPANDABLE IN DEPTH AND WIDTH
周期时间:10 nsJESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:14 mm
内存密度:4718592 bit内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:64字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

IDT72V2105L10PFG8 数据手册

 浏览型号IDT72V2105L10PFG8的Datasheet PDF文件第2页浏览型号IDT72V2105L10PFG8的Datasheet PDF文件第3页浏览型号IDT72V2105L10PFG8的Datasheet PDF文件第4页浏览型号IDT72V2105L10PFG8的Datasheet PDF文件第5页浏览型号IDT72V2105L10PFG8的Datasheet PDF文件第6页浏览型号IDT72V2105L10PFG8的Datasheet PDF文件第7页 
3.3 VOLT HIGH DENSITY CMOS  
SUPERSYNC FIFO™  
131,072 x 18  
IDT72V295  
IDT72V2105  
262,144 x 18  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
Independent Read and Write clocks (permit reading and writing  
simultaneously)  
Available in the 64-pin Thin Quad Flat Pack (TQFP)  
High-performance submicron CMOS technology  
FEATURES:  
Choose among the following memory organizations:  
IDT72V295  
IDT72V2105  
131,072 x 18  
262,144 x 18  
Pin-compatible with the IDT72V255/72V265 and the IDT72V275/  
72V285 SuperSync FIFOs  
10ns read/write cycle time (6.5ns access time)  
Fixed, low first word data latency time  
5V input tolerant  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
DESCRIPTION:  
The IDT72V295/72V2105 are exceptionally deep, high speed, CMOS  
First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These  
FIFOsoffernumerousimprovementsoverpreviousSuperSyncFIFOs,includ-  
ing the following:  
Partial Reset clears data, but retains programmable settings  
Retransmit operation with fixed, low first word data latency time  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of two preselected offsets  
The limitationofthe frequencyofone clockinputwithrespecttothe other  
has been removed. The Frequency Select pin (FS) has been removed,  
Program partial flags by either serial or parallel means  
FUNCTIONAL BLOCK DIAGRAM  
D0 -D17  
WEN  
WCLK  
LD  
SEN  
OFFSET REGISTER  
INPUT REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
HF  
FWFT/SI  
RAM ARRAY  
131,072 x 18  
262,144 x 18  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
RT  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
4668 drw 01  
Q0 -Q17  
OE  
IDT, IDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.  
OCTOBER 2008  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4668/4  

IDT72V2105L10PFG8 替代型号

型号 品牌 替代类型 描述 数据表
IDT72V2105L10PFG IDT

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