Datasheet > IDT72T3695L7BBI

IDT72T3695L7BBI

更新时间： 2024-11-11 21:57:59

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
57页	550K
描述
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

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IDT72T3695L7BBI 数据手册

2.5 VOLT HIGH-SPEED TeraSync^TMFIFO 36-BIT CONFIGURATIONS

1,024 x 36, 2,048 x 36, 4,096 x 36,

8,192 x 36, 16,384 x 36, 32,768 x 36,

65,536 x 36, 131,072 x 36 and 262,144 x 36

IDT72T3645, IDT72T3655, IDT72T3665,

IDT72T3675, IDT72T3685, IDT72T3695,

IDT72T36105, IDT72T36115, IDT72T36125

FEATURES:

Empty and Almost-Full flags

• Choose among the following memory organizations:

• Separate SCLK input for Serial programming of flag offsets

• User selectable input and output port bus-sizing

- x36 in to x36 out

- x36 in to x18 out

- x36 in to x9 out

IDT72T3645

IDT72T3655

IDT72T3665

IDT72T3675

IDT72T3685

IDT72T3695

IDT72T36105

IDT72T36115

IDT72T36125



1,024 x 36

2,048 x 36

4,096 x 36

8,192 x 36

16,384 x 36

32,768 x 36

65,536 x 36

131,072 x 36

262,144 x 36

- x18 in to x36 out

- x9 in to x36 out

• Big-Endian/Little-Endian user selectable byte representation

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Empty, Full and Half-Full flags signal FIFO status

• Up to 225 MHz Operation of Clocks

• User selectable HSTL/LVTTL Input and/or Output

• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage • Select IDT Standard timing (using EF and FF flags) or First Word

• 3.3V Input tolerant Fall Through timing (using OR and IR flags)

• Read Enable & Read Clock Echo outputs aid high speed operation • Output enable puts data outputs into high impedance state

• User selectable Asynchronous read and/or write port timing

• Mark & Retransmit, resets read pointer to user marked position

• Write Chip Select (WCS) input enables/disables Write operations

• Read Chip Select (RCS) synchronous to RCLK

• JTAG port, provided for Boundary Scan function

• Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm)

Plastic Ball Grid Array (PBGA)

• Easily expandable in depth and width

• Programmable Almost-Empty and Almost-Full flags, each flag can • Independent Read and Write Clocks (permit reading and writing

default to one of eight preselected offsets

simultaneously)

• Program programmable flags by either serial or parallel means

• Selectable synchronous/asynchronous timing modes for Almost-

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

FUNCTIONALBLOCKDIAGRAM

-Dn

(x36, x18 or x9)

LD SEN

SCLK

WEN

WCLK/WR

WCS

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FWFT/SI

PFM

FSEL0

FSEL1

WRITE CONTROL

LOGIC

ASYW

FLAG

LOGIC

RAM ARRAY

1,024 x 36, 2,048 x 36

4,096 x 36, 8,192 x 36

16,384 x 36, 32,768 x 36

65,536 x 36, 131,072 x36

262,144 x 36

WRITE POINTER

CONTROL

LOGIC

READ POINTER

BUS

CONFIGURATION

READ

CONTROL

LOGIC

MARK

ASYR

MRS

PRS

OUTPUT REGISTER

RESET

LOGIC

TCK

TRST

TMS

TDO

JTAG CONTROL

(BOUNDARY SCAN)

RCLK/RD

REN

RCS

TDI

Vref

WHSTL

RHSTL

SHSTL

HSTL I/0

CONTROL

EREN

5907 drw01

Q0 -Qn (x36, x18 or x9)

ERCLK

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

SEPTEMBER 2003



DSC-5907/17

12 3 4 5 6 7...57

中文翻译

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与IDT72T3695L7BBI相关器件

型号	品牌	获取价格	描述	数据表
IDT72T40108	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40108L10BB	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40108L10BBI	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40108L4BB	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40108L4BBG	IDT	获取价格	FIFO, 64KX40, 3.2ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
IDT72T40108L4BBI	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40108L5BB	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40108L5BBG	IDT	获取价格	FIFO, 64KX40, 3.6ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
IDT72T40108L5BBI	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40108L6.7BB	IDT	获取价格	FIFO, 64KX40, 3.8ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208

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