IDT72T40118L10BB

更新时间： 2024-09-22 22:57:23

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片双倍数据速率
页数	文件大小	规格书
52页	492K
描述
2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION

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中文翻译

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数据手册

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IDT72T40118L10BB 数据手册

2.5VOLTHIGH-SPEEDTeraSync™DDR/SDRFIFO40-BITCONFIGURATION

16,384 x 40, 32,768 x 40,

65,536 x 40, 131,072 x 40

IDT72T4088, IDT72T4098

IDT72T40108, IDT72T40118

can default to one of four preselected offsets

FEATURES

• Dedicated serial clock input for serial programming of flag offsets

• User selectable input and output port bus sizing

-x40 in to x40 out

-x40 in to x20 out

-x40 in to x10 out

-x20 in to x40 out

-x10 in to x40 out

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Choose among the following memory organizations:

IDT72T4088

IDT72T4098

IDT72T40108

IDT72T40118



16,384 x 40

32,768 x 40

65,536 x 40

131,072 x 40

• Up to 250MHz Operation of Clocks

-4ns read/write cycle time, 3.2ns access time

• Users selectable input port to output port data rates, 500Mb/s

Data Rate

• Partial Reset clears data, but retains programmable settings

• Empty and Full flags signal FIFO status

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into High-Impedance state

• JTAG port, provided for Boundary Scan function

• 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch

• Easily expandable in depth and width

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

-DDR to DDR

-DDR to SDR

-SDR to DDR

-SDR to SDR

• User selectable HSTL or LVTTL I/Os

• Read Enable & Read Clock Echo outputs aid high speed operation

• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

• 3.3V Input tolerant

• Mark & Retransmit, resets read pointer to user marked position

• Write Chip Select (WCS) input enables/disables Write

Operations

• High-performance submicron CMOS technology

• Industrial temperature range (-40°C to +85°C) is available

• Read Chip Select (RCS) synchronous to RCLK

• Programmable Almost-Empty and Almost-Full flags, each flag

FUNCTIONALBLOCKDIAGRAM

D0 -Dn (x40, x20, x10)

SREN SEN

SCLK

WCLK

WSDR

WEN

WCS

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

WRITE CONTROL

LOGIC

FLAG

LOGIC

FWFT

FSEL0

FSEL1

RAM ARRAY

16,384 x 40,

32,768 x 40

65,536 x 40

131,072 x 40

WRITE POINTER

READ POINTER

BUS

CONFIGURATION

READ

CONTROL

LOGIC

MARK

RSDR

MRS

PRS

OUTPUT REGISTER

RESET

LOGIC

TCK

TRST

TMS

TDO

JTAG CONTROL

(BOUNDARY SCAN)

RCLK

REN

RCS

TDI

Vref

HSTL I/0

CONTROL

EREN

5995 drw01

HSTL

Q0 -Qn (x40, x20, x10)

ERCLK

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheTeraSyncisatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DECEMBER 2003



DSC-5995/8

12 3 4 5 6 7...52

中文翻译

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与IDT72T40118L10BB相关器件

型号	品牌	获取价格	描述	数据表
IDT72T40118L10BBG	IDT	获取价格	暂无描述
IDT72T40118L10BBI	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40118L4BB	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40118L4BBG	IDT	获取价格	FIFO, 128KX40, 3.2ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
IDT72T40118L4BBI	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40118L5BB	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40118L5BBI	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
IDT72T40118L6.7BB	IDT	获取价格	FIFO, 128KX40, 3.8ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
IDT72T40118L6.7BBI	IDT	获取价格	FIFO, 128KX40, 3.8ns, Synchronous, CMOS, PBGA208, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-208
IDT72T40118L6-7BB	IDT	获取价格	2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION

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