2.5VOLTHIGH-SPEEDTeraSync™DDR/SDRFIFO40-BITCONFIGURATION
16,384 x 40, 32,768 x 40,
65,536 x 40, 131,072 x 40
IDT72T4088, IDT72T4098
IDT72T40108, IDT72T40118
can default to one of four preselected offsets
FEATURES
• Dedicated serial clock input for serial programming of flag offsets
• User selectable input and output port bus sizing
-x40 in to x40 out
-x40 in to x20 out
-x40 in to x10 out
-x20 in to x40 out
-x10 in to x40 out
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Choose among the following memory organizations:
IDT72T4088
IDT72T4098
IDT72T40108
IDT72T40118
16,384 x 40
32,768 x 40
65,536 x 40
131,072 x 40
• Up to 250MHz Operation of Clocks
-4ns read/write cycle time, 3.2ns access time
• Users selectable input port to output port data rates, 500Mb/s
Data Rate
• Partial Reset clears data, but retains programmable settings
• Empty and Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into High-Impedance state
• JTAG port, provided for Boundary Scan function
• 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
• User selectable HSTL or LVTTL I/Os
• Read Enable & Read Clock Echo outputs aid high speed operation
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input enables/disables Write
Operations
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag
FUNCTIONALBLOCKDIAGRAM
D0 -Dn (x40, x20, x10)
SREN SEN
SCLK
WCLK
WSDR
WEN
WCS
SI
SO
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
WRITE CONTROL
LOGIC
FLAG
LOGIC
FWFT
FSEL0
FSEL1
RAM ARRAY
16,384 x 40,
32,768 x 40
65,536 x 40
131,072 x 40
WRITE POINTER
READ POINTER
BM
IW
OW
BUS
CONFIGURATION
RT
READ
CONTROL
LOGIC
MARK
RSDR
MRS
PRS
OUTPUT REGISTER
RESET
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
RCLK
REN
RCS
TDI
Vref
HSTL I/0
CONTROL
EREN
OE
5995 drw01
HSTL
Q0 -Qn (x40, x20, x10)
ERCLK
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheTeraSyncisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DECEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5995/8