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IDT72215LB25PF PDF预览

IDT72215LB25PF

更新时间： 2024-11-20 22:39:23
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
16页 185K
描述
CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

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中文翻译

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IDT72215LB25PF 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, TQFP-64针数：64
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.37
最长访问时间：15 ns最大时钟频率 (fCLK)：40 MHz
周期时间：25 nsJESD-30 代码：S-PQFP-G64
JESD-609代码：e0长度：14 mm
内存密度：9216 bit内存集成电路类型：OTHER FIFO
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：64
字数：512 words字数代码：512
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512X18
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP64,.66SQ,32封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.005 A子类别：FIFOs
最大压摆率：0.06 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：14 mmBase Number Matches：1

IDT72215LB25PF 数据手册

 浏览型号IDT72215LB25PF的Datasheet PDF文件第2页浏览型号IDT72215LB25PF的Datasheet PDF文件第3页浏览型号IDT72215LB25PF的Datasheet PDF文件第4页浏览型号IDT72215LB25PF的Datasheet PDF文件第5页浏览型号IDT72215LB25PF的Datasheet PDF文件第6页浏览型号IDT72215LB25PF的Datasheet PDF文件第7页 
IDT72205LB  
IDT72215LB  
IDT72225LB  
IDT72235LB  
IDT72245LB  
CMOS SyncFIFO™  
256 x 18, 512 x 18, 1,024 x 18,  
2,048 x 18 and 4,096 x 18  
Integrated Device Technology, Inc.  
are applicable for a wide variety of data buffering needs, such  
as optical disk controllers, Local Area Networks (LANs), and  
interprocessor communication.  
FEATURES:  
• 256 x 18-bit organization array (IDT72205LB)  
• 512 x 18-bit organization array (IDT72215LB)  
• 1,024 x 18-bit organization array (IDT72225LB)  
• 2,048 x 18-bit organization array (IDT72235LB)  
• 4,096 x 18-bit organization array (IDT72245LB)  
• 10 ns read/write cycle time  
• Empty and Full flags signal FIFO status  
• Easily expandable in depth and width  
• Asynchronous or coincident read and write clocks  
• Programmable Almost-Empty and Almost-Full flags with  
default settings  
These FIFOs have 18-bit input and output ports. The input  
port is controlled by a free-running clock (WCLK), and an input  
enable pin (WEN). Data is read into the synchronous FIFO on  
everyclockwhenWEN isasserted.Theoutputportiscontrolled  
byanotherclockpin(RCLK)andanotherenablepin(REN).The  
read clock can be tied to the write clock for single clock  
operation or the two clocks can run asynchronous of one  
another for dual-clock operation. An Output Enable pin (OE) is  
provided on the read port for three-state control of the output.  
ThesynchronousFIFOshavetwofixedflags,Empty(EF)and  
Full (FF), and two programmable flags, Almost-Empty (PAE)  
and Almost-Full (PAF). The offset loading of the programmable  
flags is controlled by a simple state machine, and is initiated by  
asserting the Load pin (LD). A Half-Full flag (HF) is available  
when the FIFO is used in a single device configuration.  
These devices are depth expandable using a Daisy-Chain  
technique. The XI and XO pins are used to expand the FIFOs.  
In depth expansion configuration, FL is grounded on the first  
deviceandsettoHIGHforallotherdevicesintheDaisyChain.  
TheIDT72205LB/72215LB/72225LB/72235LB/72245LBis  
fabricated using IDT’s high-speed submicron CMOS technol-  
ogy.  
• Half-Full flag capability  
• Dual-Port zero fall-through time architecture  
• Output enable puts output data bus in high-impedance  
state  
• High-performance submicron CMOS technology  
• Available in a 64-lead thin quad flatpack (TQFP/STQFP)  
and plastic leaded chip carrier (PLCC)  
• Industrial temperature range (–40°C to +85°C) is available  
DESCRIPTION:  
The IDT72205LB/72215LB/72225LB/72235LB/72245LB  
are very high-speed, low-power First-In, First-Out (FIFO)  
memories with clocked read and write controls. These FIFOs  
FUNCTIONAL BLOCK DIAGRAM  
WCLK  
D0-D17  
INPUT REGISTER  
OFFSET REGISTER  
FLAG  
WRITE CONTROL  
LOGIC  
•
•
LOGIC  
RAM ARRAY  
256 x 18, 512 x 18  
1,024 x 18, 2,048 x 18  
4,096 x 18  
)
READ POINTER  
WRITE POINTER  
•
•
READ CONTROL  
LOGIC  
EXPANSION LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
2766 drw 01  
RCLK  
Q0-Q17  
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2000  
©2000 Integrated Device Technology, Inc.  
DSC-2766/-  
1
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.  
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中文翻译

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IDT72215LB25PF 替代型号

型号 品牌 替代类型 描述 数据表
72215LB25JI IDT

功能相似

 PLCC-68, Tube
IDT72215LB25PFI IDT

功能相似

 CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

与IDT72215LB25PF相关器件

型号 品牌 获取价格 描述 数据表
IDT72215LB25PF8 IDT

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 		FIFO, 512X18, 15ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72215LB25PFB IDT

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 		CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB25PFG IDT

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 		FIFO, 512X18, 15ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
IDT72215LB25PFGI IDT

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 		FIFO, 512X18, 15ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
IDT72215LB25PFGI8 IDT

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 		FIFO, 512X18, 15ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72215LB25PFI IDT

获取价格

 		CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB25PFI8 IDT

获取价格

 		FIFO, 512X18, 15ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72215LB25PFI9 IDT

获取价格

 		FIFO, 512X18, 15ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72215LB25TF IDT

获取价格

 		CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB25TF8 IDT

获取价格

 		FIFO, 512X18, 15ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64

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