5秒后页面跳转
IDT72215LB35TF PDF预览

IDT72215LB35TF

更新时间: 2024-11-11 23:01:15
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
16页 185K
描述
CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

IDT72215LB35TF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:STQFP-64
针数:64Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.75最长访问时间:20 ns
最大时钟频率 (fCLK):28.6 MHz周期时间:35 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:9216 bit
内存集成电路类型:OTHER FIFO内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:64字数:512 words
字数代码:512工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512X18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.005 A
子类别:FIFOs最大压摆率:0.06 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

IDT72215LB35TF 数据手册

 浏览型号IDT72215LB35TF的Datasheet PDF文件第2页浏览型号IDT72215LB35TF的Datasheet PDF文件第3页浏览型号IDT72215LB35TF的Datasheet PDF文件第4页浏览型号IDT72215LB35TF的Datasheet PDF文件第5页浏览型号IDT72215LB35TF的Datasheet PDF文件第6页浏览型号IDT72215LB35TF的Datasheet PDF文件第7页 
IDT72205LB  
IDT72215LB  
IDT72225LB  
IDT72235LB  
IDT72245LB  
CMOS SyncFIFO™  
256 x 18, 512 x 18, 1,024 x 18,  
2,048 x 18 and 4,096 x 18  
Integrated Device Technology, Inc.  
are applicable for a wide variety of data buffering needs, such  
as optical disk controllers, Local Area Networks (LANs), and  
interprocessor communication.  
FEATURES:  
• 256 x 18-bit organization array (IDT72205LB)  
• 512 x 18-bit organization array (IDT72215LB)  
• 1,024 x 18-bit organization array (IDT72225LB)  
• 2,048 x 18-bit organization array (IDT72235LB)  
• 4,096 x 18-bit organization array (IDT72245LB)  
• 10 ns read/write cycle time  
• Empty and Full flags signal FIFO status  
• Easily expandable in depth and width  
• Asynchronous or coincident read and write clocks  
• Programmable Almost-Empty and Almost-Full flags with  
default settings  
These FIFOs have 18-bit input and output ports. The input  
port is controlled by a free-running clock (WCLK), and an input  
enable pin (WEN). Data is read into the synchronous FIFO on  
everyclockwhenWEN isasserted.Theoutputportiscontrolled  
byanotherclockpin(RCLK)andanotherenablepin(REN).The  
read clock can be tied to the write clock for single clock  
operation or the two clocks can run asynchronous of one  
another for dual-clock operation. An Output Enable pin (OE) is  
provided on the read port for three-state control of the output.  
ThesynchronousFIFOshavetwofixedflags,Empty(EF)and  
Full (FF), and two programmable flags, Almost-Empty (PAE)  
and Almost-Full (PAF). The offset loading of the programmable  
flags is controlled by a simple state machine, and is initiated by  
asserting the Load pin (LD). A Half-Full flag (HF) is available  
when the FIFO is used in a single device configuration.  
These devices are depth expandable using a Daisy-Chain  
technique. The XI and XO pins are used to expand the FIFOs.  
In depth expansion configuration, FL is grounded on the first  
deviceandsettoHIGHforallotherdevicesintheDaisyChain.  
TheIDT72205LB/72215LB/72225LB/72235LB/72245LBis  
fabricated using IDT’s high-speed submicron CMOS technol-  
ogy.  
• Half-Full flag capability  
• Dual-Port zero fall-through time architecture  
• Output enable puts output data bus in high-impedance  
state  
• High-performance submicron CMOS technology  
• Available in a 64-lead thin quad flatpack (TQFP/STQFP)  
and plastic leaded chip carrier (PLCC)  
• Industrial temperature range (–40°C to +85°C) is available  
DESCRIPTION:  
The IDT72205LB/72215LB/72225LB/72235LB/72245LB  
are very high-speed, low-power First-In, First-Out (FIFO)  
memories with clocked read and write controls. These FIFOs  
FUNCTIONAL BLOCK DIAGRAM  
WCLK  
D0-D17  
INPUT REGISTER  
OFFSET REGISTER  
FLAG  
WRITE CONTROL  
LOGIC  
LOGIC  
RAM ARRAY  
256 x 18, 512 x 18  
1,024 x 18, 2,048 x 18  
4,096 x 18  
)
READ POINTER  
WRITE POINTER  
READ CONTROL  
LOGIC  
EXPANSION LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
2766 drw 01  
RCLK  
Q0-Q17  
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2000  
©2000 Integrated Device Technology, Inc.  
DSC-2766/-  
1
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.  

与IDT72215LB35TF相关器件

型号 品牌 获取价格 描述 数据表
IDT72215LB35TFB IDT

获取价格

CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB50F IDT

获取价格

FIFO, 512X18, 25ns, Synchronous, CMOS, QFP-68
IDT72215LB50G IDT

获取价格

CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB50GB IDT

获取价格

CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB50J IDT

获取价格

CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB50JB IDT

获取价格

CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB50PF IDT

获取价格

CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB50PFB IDT

获取价格

CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB50TF IDT

获取价格

CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72215LB50TFB IDT

获取价格

CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18