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IDT72215LB25JG PDF预览

IDT72215LB25JG

更新时间: 2024-11-21 19:52:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
16页 157K
描述
FIFO, 512X18, 15ns, Synchronous, CMOS, PQCC68, GREEN, PLASTIC, LCC-68

IDT72215LB25JG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ, LDCC68,1.0SQ针数:68
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.22
最长访问时间:15 ns最大时钟频率 (fCLK):40 MHz
周期时间:25 nsJESD-30 代码:S-PQCC-J68
JESD-609代码:e3长度:24.2062 mm
内存密度:9216 bit内存集成电路类型:OTHER FIFO
内存宽度:18湿度敏感等级:1
功能数量:1端子数量:68
字数:512 words字数代码:512
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512X18
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:4.572 mm
最大待机电流:0.005 A子类别:FIFOs
最大压摆率:0.06 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:24.2062 mmBase Number Matches:1

IDT72215LB25JG 数据手册

 浏览型号IDT72215LB25JG的Datasheet PDF文件第2页浏览型号IDT72215LB25JG的Datasheet PDF文件第3页浏览型号IDT72215LB25JG的Datasheet PDF文件第4页浏览型号IDT72215LB25JG的Datasheet PDF文件第5页浏览型号IDT72215LB25JG的Datasheet PDF文件第6页浏览型号IDT72215LB25JG的Datasheet PDF文件第7页 
CMOS SyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18,  
2,048 x 18, and 4,096 x 18  
IDT72205LB, IDT72215LB,  
IDT72225LB, IDT72235LB,  
IDT72245LB  
writecontrols.TheseFIFOsareapplicableforawidevarietyofdatabuffering  
needs, such as optical disk controllers, Local Area Networks (LANs), and  
interprocessorcommunication.  
FEATURES:  
256 x 18-bit organization array (IDT72205LB)  
512 x 18-bit organization array (IDT72215LB)  
1,024 x 18-bit organization array (IDT72225LB)  
2,048 x 18-bit organization array (IDT72235LB)  
4,096 x 18-bit organization array (IDT72245LB)  
10 ns read/write cycle time  
TheseFIFOshave18-bitinputandoutputports.Theinputportiscontrolled  
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread  
intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput  
portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).  
Thereadclockcanbetiedtothewriteclockforsingleclockoperationorthe  
twoclockscanrunasynchronousofoneanotherfordual-clockoperation. An  
OutputEnablepin(OE)isprovidedonthereadportforthree-statecontrolof  
theoutput.  
Thesynchronous FIFOs havetwofixedflags,Empty (EF)andFull(FF),  
andtwoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF).The  
offsetloadingoftheprogrammableflagsiscontrolledbyasimplestatemachine,  
andisinitiatedbyassertingtheLoadpin(LD). AHalf-Fullflag(HF)isavailable  
when the FIFO is used in a single device configuration.  
ThesedevicesaredepthexpandableusingaDaisy-Chaintechnique.The  
XI andXO pins are usedtoexpandthe FIFOs. Indepthexpansionconfigu-  
ration, FirstLoad(FL)is groundedonthe firstdevice andsettoHIGHforall  
other devices in the Daisy Chain.  
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated  
usingIDT’shigh-speedsubmicronCMOStechnology.  
Empy and Full flags signal FIFO status  
Easy expandable in depth and width  
Asynchronous or coincident read and write clocks  
Programmable Almost-Empty and Almost-Full flags with  
default settings  
Half-Full flag capability  
Dual-Port zero fall-through time architecture  
Output enable puts output data bus in high-impedence state  
High-performance submicron CMOS technology  
Available in a 64-lead thin quad flatpack (TQFP/STQFP)  
and plastic leaded chip carrier (PLCC)  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
DESCRIPTION:  
The IDT72205LB/72215LB/72225LB/72235LB/72245LBare very high  
speed,low-powerFirst-In,First-Out(FIFO)memorieswithclockedreadand  
FUNCTIONAL BLOCK DIAGRAM  
WCLK  
D0-D17  
INPUT REGISTER  
OFFSET REGISTER  
FLAG  
WRITE CONTROL  
LOGIC  
LOGIC  
RAM ARRAY  
256 x 18, 512 x 18  
1,024 x 18, 2,048 x 18  
4,096 x 18  
)
READ POINTER  
WRITE POINTER  
READ CONTROL  
LOGIC  
EXPANSION LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
2766 drw 01  
RCLK  
Q0-Q17  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology, Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.  
OCTOBER 2006  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
©2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-2766/1  

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