Datasheet > IDT71V67703S85PFI8

IDT71V67703S85PFI8

更新时间： 2024-02-19 21:28:17

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
23页	511K
描述
Cache SRAM, 256KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM, PLASTIC, TQFP-100

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IDT71V67703S85PFI8 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM, PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.28	Is Samacsys：	N
最长访问时间：	8.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	87 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	256KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.07 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.21 mA
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	14 mm
Base Number Matches：	1

IDT71V67703S85PFI8 数据手册

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IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Flow-Through Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

PinDefinitions⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

A⁰-A¹⁸

Address Inputs

N/A

Synchronous Address inputs. The address register is triggered by a combi-nation of the

rising edge of CLK and ADSC Low or ADSP Low and CE Low.

Address Status

(Cache Controller)

LOW

Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is

used to load the address registers with new addresses.

ADSC

ADSP

ADV

Address Status

(Processor)

Synchronous Address Status from Processor. ADSP is an active LOW input that is used to

load the address registers with new addresses.

is gated by

ADSP

Burst Address

Advance

Synchronous Address Advance. ADV is an active LOW input that is used to advance the

internal burst counter, controlling burst access after the initial address is loaded. When the

input is HIGH the burst counter is not incremented; that is, there is no address advance.

Byte Write Enable

LOW

Synchronous byte write enable gates the byte write inputs BW¹-BW⁴. If BWE is LOW at the

rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is

HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.

BWE

Individual Byte

Write Enables

LOW

N/A

Synchronous byte write enables. BW¹controls I/O^0-7, I/O^P1, BW²controls I/O^8-15, I/O^P2, etc.

Any active byte write causes all outputs to be disabled.

BW¹-BW4

Chip Enable

Synchronous chip enable. CE is used with CS⁰and CS¹to enable the IDT71V67703/7903.

CE also gates ADSP.

CLK

Clock

This is the clock input. All timing references for the device are made with respect to this

input.

CS⁰

CS1

Chip Select 0

Chip Select 1

HIGH

LOW

Synchronous active HIGH chip select. CS⁰is used with CE and CS¹to enable the chip.

Synchronous active LOW chip select. CS¹is used with CE and CS⁰to enable the chip.

Global Write

Enable

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW

on the rising edge of CLK. GW supersedes individual byte write enables.

I/O⁰-I/O³¹

I/O^P1-I/O^P4

Data Input/Output

I/O

N/A

Synchronous data input/output (I/O) pins. The data input path is registered, triggered by

the rising edge of CLK. The data output path is flow-through (no output register).

Linear Burst Order

LOW

Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst

sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a

static input and must not change state while the device is operating.

LBO

Output Enable

LOW

Asynchronous output enable. When OE is LOW the data output drivers are enabled on the

I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-

impedance state.

V^DD

V^DDQ

V^SS

Power Supply

Ground

N/A

3.3V core power supply.

3.3V I/O Supply.

N/A

Ground.

No Connect

Sleep Mode

N/A

NC pins are not electrically connected to the device.

HIGH

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down

the IDT71V67703/7903 to its lowest power consumption level. Data retention is guaranteed

in Sleep Mode.

5309 tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.422

123 4 5 6 7...23

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IDT71V67802	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802133BG	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802133BGI	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802133BQ	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802133BQI	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802133PF	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格

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