Datasheet > IDT71V67802150PF

IDT71V67802150PF

更新时间： 2022-11-27 00:51:34

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
23页	515K
描述
256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect

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IDT71V67802150PF 数据手册

256K X 36, 512K X 18

3.3VSynchronousSRAMs

2.5V I/O, Burst Counter

IDT71V67602

IDT71V67802

PipelinedOutputs,SingleCycleDeselect

Features

Description

◆

256K x 36, 512K x 18 memory configurations

Supports high system speed:

The IDT71V67602/7802 are high-speed SRAMs organized as

256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

◆

LBO input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O supply (VDDQ)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array.

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V67602/7802canprovidefourcyclesof

dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

andthe LBO inputpin.

◆

TheIDT71V67602/7802SRAMsutilizeIDT’slatesthigh-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

A0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CS , CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

(1)

BW , BW , BW , BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O0-I/O31, I/OP1-I/OP4

VDD, VDDQ

VSS

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

5311 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V67802.

NOVEMBER 2002

DSC-5311/05

12 3 4 5 6 7...23

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与IDT71V67802150PF相关器件

型号	品牌	描述	获取价格	数据表
IDT71V67802150PFI	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802166BG	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802166BGI	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802166BQ	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802166BQI	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格
IDT71V67802166PF	IDT	256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin	获取价格

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