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IDT71V421S35PFI PDF预览

IDT71V421S35PFI

更新时间: 2024-11-04 22:36:23
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
14页 130K
描述
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT

IDT71V421S35PFI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:QFP, QFP64,.66SQ,32
Reach Compliance Code:not_compliant风险等级:5.92
最长访问时间:35 nsI/O 类型:COMMON
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
内存密度:16384 bit内存集成电路类型:MULTI-PORT SRAM
内存宽度:8湿度敏感等级:3
端口数量:2端子数量:64
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP64,.66SQ,32
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.005 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.125 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20Base Number Matches:1

IDT71V421S35PFI 数据手册

 浏览型号IDT71V421S35PFI的Datasheet PDF文件第2页浏览型号IDT71V421S35PFI的Datasheet PDF文件第3页浏览型号IDT71V421S35PFI的Datasheet PDF文件第4页浏览型号IDT71V421S35PFI的Datasheet PDF文件第5页浏览型号IDT71V421S35PFI的Datasheet PDF文件第6页浏览型号IDT71V421S35PFI的Datasheet PDF文件第7页 
IDT71V321S/L  
IDT71V421S/L  
HIGH SPEED 3.3V  
2K X 8 DUAL-PORT  
STATIC RAM WITH INTERRUPTS  
ꢀeatures  
MASTER IDT71V321 easily expands data bus width to 16-  
or-more-bits using SLAVE IDT71V421  
High-speed access  
– Commercial: 25/35/55ns (max.)  
Industrial: 25ns (max.)  
Low-power operation  
On-chip port arbitration logic (IDT71V321 only)  
BUSY output flag on IDT71V321; BUSY input on IDT71V421  
Fully asynchronous operation from either port  
Battery backup operation2V data retention (L only)  
TTL-compatible, single 3.3V power supply  
Available in 52-pin PLCC, 64-pin TQFP and STQFP  
packages  
IDT71V321/IDT71V421S  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
IDT71V321/V421L  
Active: 325mW (typ.)  
Standby: 1mW (typ.)  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Two INT flags for port-to-port communications  
ꢀunctionalBlockDiagram  
OER  
OEL  
CER  
CEL  
R/WR  
R/WL  
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSYR  
BUSYL  
A10L  
A0L  
A10R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0R  
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CEL  
OEL  
CER  
OER  
R/WR  
R/WL  
(2)  
(2)  
INTL  
INTR  
3026 drw 01  
NOTES:  
1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.  
2. BUSY and INT are totem-pole outputs.  
AUGUST 2001  
1
DSC-3026/8  
©2001IntegratedDeviceTechnology,Inc.  

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