IDT71V421S55JI

更新时间： 2024-11-05 22:36:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
14页	130K
描述
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT

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中文翻译

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技术参数
数据手册

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IDT71V421S55JI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	QCCJ, LDCC52,.8SQ
Reach Compliance Code：	not_compliant	风险等级：	5.92
Base Number Matches：	1

IDT71V421S55JI 数据手册

IDT71V321S/L

IDT71V421S/L

HIGH SPEED 3.3V

2K X 8 DUAL-PORT

STATIC RAM WITH INTERRUPTS

ꢀeatures

◆

MASTER IDT71V321 easily expands data bus width to 16-

or-more-bits using SLAVE IDT71V421

High-speed access

– Commercial: 25/35/55ns (max.)

– Industrial: 25ns (max.)

Low-power operation

◆

On-chip port arbitration logic (IDT71V321 only)

BUSY output flag on IDT71V321; BUSY input on IDT71V421

Fully asynchronous operation from either port

Battery backup operation—2V data retention (L only)

TTL-compatible, single 3.3V power supply

Available in 52-pin PLCC, 64-pin TQFP and STQFP

packages

◆

– IDT71V321/IDT71V421S

— Active: 325mW (typ.)

— Standby: 5mW (typ.)

– IDT71V321/V421L

— Active: 325mW (typ.)

— Standby: 1mW (typ.)

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Two INT flags for port-to-port communications

ꢀunctionalBlockDiagram

OER

OEL

CER

CEL

R/WR

R/WL

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

I/O

Control

(1,2)

BUSYR

BUSYL

A10L

A0L

A10R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0R

ARBITRATION

and

INTERRUPT

LOGIC

CE_L

OE_L

CER

OER

R/WR

R/WL

(2)

INTL

INTR

3026 drw 01

NOTES:

1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.

2. BUSY and INT are totem-pole outputs.

AUGUST 2001

DSC-3026/8

12 3 4 5 6 7...14

中文翻译

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